{ "Info" "IFLOW_SR_FILE_CHANGED_BASE" "" "Detected changes in source files." { { "Info" "IFLOW_SR_FILE_CHANGED" "/mnt/hgfs/vhdl/RX_TX.vhd " "Source file: /mnt/hgfs/vhdl/RX_TX.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Quartus II" 0 -1 1388350910032 ""} } { } 0 293032 "Detected changes in source files." 0 0 "Quartus II" 0 -1 1388350910032 ""} { "Info" "IFLOW_SR_FILE_CHANGED_BASE" "" "Detected changes in source files." { { "Info" "IFLOW_SR_FILE_CHANGED" "/mnt/hgfs/vhdl/RX_TX.vhd " "Source file: /mnt/hgfs/vhdl/RX_TX.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Quartus II" 0 -1 1388350910049 ""} } { } 0 293032 "Detected changes in source files." 0 0 "Quartus II" 0 -1 1388350910049 ""} { "Info" "IFLOW_SR_FILE_CHANGED_BASE" "" "Detected changes in source files." { { "Info" "IFLOW_SR_FILE_CHANGED" "/mnt/hgfs/vhdl/RX_TX.vhd " "Source file: /mnt/hgfs/vhdl/RX_TX.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Quartus II" 0 -1 1388350910065 ""} } { } 0 293032 "Detected changes in source files." 0 0 "Quartus II" 0 -1 1388350910065 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1388350914188 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1388350914192 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 29 22:01:53 2013 " "Processing started: Sun Dec 29 22:01:53 2013" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1388350914192 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1388350914192 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sk610-delay -c sk610-delay " "Command: quartus_map --read_settings_files=on --write_settings_files=off sk610-delay -c sk610-delay" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1388350914193 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1388350914622 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RX_TX.vhd 2 1 " "Found 2 design units, including 1 entities, in source file RX_TX.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RX_TX-RX_TX_arch " "Found design unit 1: RX_TX-RX_TX_arch" { } { { "RX_TX.vhd" "" { Text "/mnt/hgfs/vhdl/RX_TX.vhd" 33 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915459 ""} { "Info" "ISGN_ENTITY_NAME" "1 RX_TX " "Found entity 1: RX_TX" { } { { "RX_TX.vhd" "" { Text "/mnt/hgfs/vhdl/RX_TX.vhd" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1388350915459 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Address_Counter.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Address_Counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Address_Counter-Address_Counter_arch " "Found design unit 1: Address_Counter-Address_Counter_arch" { } { { "Address_Counter.vhd" "" { Text "/mnt/hgfs/vhdl/Address_Counter.vhd" 30 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915468 ""} { "Info" "ISGN_ENTITY_NAME" "1 Address_Counter " "Found entity 1: Address_Counter" { } { { "Address_Counter.vhd" "" { Text "/mnt/hgfs/vhdl/Address_Counter.vhd" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915468 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1388350915468 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Ram_Control.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Ram_Control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Ram_Control-Ram_Control_arch " "Found design unit 1: Ram_Control-Ram_Control_arch" { } { { "Ram_Control.vhd" "" { Text "/mnt/hgfs/vhdl/Ram_Control.vhd" 52 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915476 ""} { "Info" "ISGN_ENTITY_NAME" "1 Ram_Control " "Found entity 1: Ram_Control" { } { { "Ram_Control.vhd" "" { Text "/mnt/hgfs/vhdl/Ram_Control.vhd" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1388350915476 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AD_DA.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AD_DA.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AD_DA-AD_DA_Arch " "Found design unit 1: AD_DA-AD_DA_Arch" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 36 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915484 ""} { "Info" "ISGN_ENTITY_NAME" "1 AD_DA " "Found entity 1: AD_DA" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915484 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1388350915484 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Top.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Top-Top_Arch " "Found design unit 1: Top-Top_Arch" { } { { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 46 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915492 ""} { "Info" "ISGN_ENTITY_NAME" "1 Top " "Found entity 1: Top" { } { { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1388350915492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1388350915492 ""} { "Info" "ISGN_START_ELABORATION_TOP" "Top " "Elaborating entity \"Top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1388350915656 ""} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "load_max Top.vhd(122) " "Verilog HDL or VHDL warning at Top.vhd(122): object \"load_max\" assigned a value but never read" { } { { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 122 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1388350915660 "|Top"} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Address_Counter Address_Counter:Address_Counter_Inst " "Elaborating entity \"Address_Counter\" for hierarchy \"Address_Counter:Address_Counter_Inst\"" { } { { "Top.vhd" "Address_Counter_Inst" { Text "/mnt/hgfs/vhdl/Top.vhd" 130 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1388350915666 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "AD_DA AD_DA:AD_DA_Inst " "Elaborating entity \"AD_DA\" for hierarchy \"AD_DA:AD_DA_Inst\"" { } { { "Top.vhd" "AD_DA_Inst" { Text "/mnt/hgfs/vhdl/Top.vhd" 142 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1388350915672 ""} { "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_Input AD_DA.vhd(45) " "VHDL Process Statement warning at AD_DA.vhd(45): signal \"AD_Input\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 45 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "da_data AD_DA.vhd(46) " "VHDL Process Statement warning at AD_DA.vhd(46): signal \"da_data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 46 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ad_data AD_DA.vhd(41) " "VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable \"ad_data\", which holds its previous value in one or more paths through the process" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DA_Out AD_DA.vhd(41) " "VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable \"DA_Out\", which holds its previous value in one or more paths through the process" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DA_Clk AD_DA.vhd(41) " "VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable \"DA_Clk\", which holds its previous value in one or more paths through the process" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "AD_Clk AD_DA.vhd(41) " "VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable \"AD_Clk\", which holds its previous value in one or more paths through the process" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AD_Clk AD_DA.vhd(41) " "Inferred latch for \"AD_Clk\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Clk AD_DA.vhd(41) " "Inferred latch for \"DA_Clk\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[0\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[0\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915675 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[1\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[1\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[2\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[2\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[3\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[3\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[4\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[4\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[5\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[5\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[6\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[6\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DA_Out\[7\] AD_DA.vhd(41) " "Inferred latch for \"DA_Out\[7\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[0\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[0\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[1\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[1\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[2\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[2\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[3\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[3\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[4\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[4\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915676 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[5\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[5\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915677 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[6\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[6\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915677 "|Top|AD_DA:AD_DA_Inst"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_data\[7\] AD_DA.vhd(41) " "Inferred latch for \"ad_data\[7\]\" at AD_DA.vhd(41)" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 41 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1388350915677 "|Top|AD_DA:AD_DA_Inst"} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Ram_Control Ram_Control:Ram_Control_Inst " "Elaborating entity \"Ram_Control\" for hierarchy \"Ram_Control:Ram_Control_Inst\"" { } { { "Top.vhd" "Ram_Control_Inst" { Text "/mnt/hgfs/vhdl/Top.vhd" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1388350915680 ""} { "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "write_buf Ram_Control.vhd(264) " "VHDL Process Statement warning at Ram_Control.vhd(264): signal \"write_buf\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "Ram_Control.vhd" "" { Text "/mnt/hgfs/vhdl/Ram_Control.vhd" 264 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Quartus II" 0 -1 1388350915683 "|Top|Ram_Control:Ram_Control_Inst"} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "RX_TX RX_TX:RX_TX_Inst " "Elaborating entity \"RX_TX\" for hierarchy \"RX_TX:RX_TX_Inst\"" { } { { "Top.vhd" "RX_TX_Inst" { Text "/mnt/hgfs/vhdl/Top.vhd" 178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1388350915687 ""} { "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "MISO RX_TX.vhd(19) " "VHDL Signal Declaration warning at RX_TX.vhd(19): used implicit default value for signal \"MISO\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "RX_TX.vhd" "" { Text "/mnt/hgfs/vhdl/RX_TX.vhd" 19 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "Quartus II" 0 -1 1388350915691 "|Top|RX_TX:RX_TX_Inst"} { "Warning" "WOPT_OPT_PROTECT_A_CLOCK_MUX" "" "Clock multiplexers are found and protected" { { "Warning" "WOPT_OPT_PROTECT_A_CLOCK_MUX_SUB" "Address_Counter:Address_Counter_Inst\|Mux0 " "Found clock multiplexer Address_Counter:Address_Counter_Inst\|Mux0" { } { { "Address_Counter.vhd" "" { Text "/mnt/hgfs/vhdl/Address_Counter.vhd" 76 -1 0 } } } 0 19017 "Found clock multiplexer %1!s!" 0 0 "Quartus II" 0 -1 1388350916035 "|Top|Address_Counter:Address_Counter_Inst|Mux0"} } { } 0 19016 "Clock multiplexers are found and protected" 0 0 "Quartus II" 0 -1 1388350916035 ""} { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1388350916684 ""} { "Info" "IMLS_MLS_DUP_LATCH_INFO_HDR" "" "Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IMLS_MLS_DUP_LATCH_INFO" "AD_DA:AD_DA_Inst\|DA_Clk AD_DA:AD_DA_Inst\|AD_Clk " "Duplicate LATCH primitive \"AD_DA:AD_DA_Inst\|DA_Clk\" merged with LATCH primitive \"AD_DA:AD_DA_Inst\|AD_Clk\"" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 28 -1 0 } } } 0 13026 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "Quartus II" 0 -1 1388350916699 ""} } { } 0 13025 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "Quartus II" 0 -1 1388350916699 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "AD_DA:AD_DA_Inst\|AD_Clk " "Latch AD_DA:AD_DA_Inst\|AD_Clk has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA Ram_Control:Ram_Control_Inst\|ram_state.precharge " "Ports D and ENA on the latch are fed by the same signal Ram_Control:Ram_Control_Inst\|ram_state.precharge" { } { { "Ram_Control.vhd" "" { Text "/mnt/hgfs/vhdl/Ram_Control.vhd" 93 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1388350916700 ""} } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 25 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1388350916700 ""} { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "Led2 GND " "Pin \"Led2\" is stuck at GND" { } { { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 19 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1388350916851 "|Top|Led2"} { "Warning" "WMLS_MLS_STUCK_PIN" "MISO GND " "Pin \"MISO\" is stuck at GND" { } { { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 36 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1388350916851 "|Top|MISO"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1388350916851 ""} { "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 121 -1 0 } } { "Ram_Control.vhd" "" { Text "/mnt/hgfs/vhdl/Ram_Control.vhd" 101 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1388350916889 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "283 " "Implemented 283 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1388350917127 ""} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Implemented 34 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1388350917127 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1388350917127 ""} { "Info" "ICUT_CUT_TM_LCELLS" "225 " "Implemented 225 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1388350917127 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1388350917127 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "360 " "Peak virtual memory: 360 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1388350917438 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 29 22:01:57 2013 " "Processing ended: Sun Dec 29 22:01:57 2013" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1388350917438 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1388350917438 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1388350917438 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1388350917438 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1388350920676 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1388350920678 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 29 22:02:00 2013 " "Processing started: Sun Dec 29 22:02:00 2013" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1388350920678 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1388350920678 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay " "Command: quartus_fit --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1388350920679 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1388350920885 ""} { "Info" "0" "" "Project = sk610-delay" { } { } 0 0 "Project = sk610-delay" 0 0 "Fitter" 0 0 1388350920887 ""} { "Info" "0" "" "Revision = sk610-delay" { } { } 0 0 "Revision = sk610-delay" 0 0 "Fitter" 0 0 1388350920887 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1388350921078 ""} { "Info" "IMPP_MPP_USER_DEVICE" "sk610-delay EPM240T100C5 " "Selected device EPM240T100C5 for design \"sk610-delay\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1388350921083 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1388350921304 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1388350921304 ""} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1388350921940 ""} { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1388350921966 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1388350922290 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1388350922290 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1388350922290 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1388350922290 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1388350922290 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1388350922290 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES" "17 " "TimeQuest Timing Analyzer is analyzing 17 combinational loops as latches." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1388350922528 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "sk610-delay.sdc " "Synopsys Design Constraints File file not found: 'sk610-delay.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1388350922550 ""} { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1388350922562 ""} { "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1388350922588 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1388350922588 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1388350922593 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1388350922593 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 Clk " " 1.000 Clk" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1388350922593 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 Ram_Control:Ram_Control_Inst\|ram_state.activate " " 1.000 Ram_Control:Ram_Control_Inst\|ram_state.activate" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1388350922593 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 V_Sync " " 1.000 V_Sync" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1388350922593 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1388350922593 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1388350922630 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1388350922638 ""} { "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1388350922663 ""} { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED" "pin Clk " "Promoted pin \"Clk\" with Global Signal logic option assignment" { { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_TO_LOCATION" "pin Clk PIN 12 " "Assigned pin \"Clk\" to location PIN 12" { } { { "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "Clk" } } } } { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 16 -1 0 } } { "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" { Clk } } } { "temporary_test_loc" "" { Generic "/mnt/hgfs/vhdl/" { { 0 { 0 ""} 0 627 9224 9983 0} } } } } 0 186213 "Assigned %1!s! \"%2!s!\" to location %3!s!" 0 0 "Quartus II" 0 -1 1388350922677 ""} { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_REGION" "Global clock the entire device " "Fan-outs that use the Global signal logic option setting Global clock are assigned to the entire device" { } { } 0 186214 "Fan-outs that use the Global signal logic option setting %1!s! are assigned to %2!s!" 0 0 "Quartus II" 0 -1 1388350922677 ""} } { { "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "Clk" } } } } { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 16 -1 0 } } { "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" { Clk } } } { "temporary_test_loc" "" { Generic "/mnt/hgfs/vhdl/" { { 0 { 0 ""} 0 627 9224 9983 0} } } } } 0 186212 "Promoted %1!s! \"%2!s!\" with Global Signal logic option assignment" 0 0 "Fitter" 0 -1 1388350922677 ""} { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED" "pin ResetN " "Promoted pin \"ResetN\" with Global Signal logic option assignment" { { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_TO_LOCATION" "pin ResetN PIN 14 " "Assigned pin \"ResetN\" to location PIN 14" { } { { "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ResetN } "NODE_NAME" } } { "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ResetN" } } } } { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 17 -1 0 } } { "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" { ResetN } } } { "temporary_test_loc" "" { Generic "/mnt/hgfs/vhdl/" { { 0 { 0 ""} 0 628 9224 9983 0} } } } } 0 186213 "Assigned %1!s! \"%2!s!\" to location %3!s!" 0 0 "Quartus II" 0 -1 1388350922679 ""} { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_REGION" "Global clock the entire device " "Fan-outs that use the Global signal logic option setting Global clock are assigned to the entire device" { } { } 0 186214 "Fan-outs that use the Global signal logic option setting %1!s! are assigned to %2!s!" 0 0 "Quartus II" 0 -1 1388350922679 ""} } { { "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/me/altera/13.0sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ResetN" } } } } { "Top.vhd" "" { Text "/mnt/hgfs/vhdl/Top.vhd" 17 -1 0 } } { "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ResetN } "NODE_NAME" } } { "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/me/altera/13.0sp1/quartus/linux/pin_planner.ppl" { ResetN } } } { "temporary_test_loc" "" { Generic "/mnt/hgfs/vhdl/" { { 0 { 0 ""} 0 628 9224 9983 0} } } } } 0 186212 "Promoted %1!s! \"%2!s!\" with Global Signal logic option assignment" 0 0 "Fitter" 0 -1 1388350922679 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rtl~0 Global clock " "Automatically promoted signal \"rtl~0\" to use Global clock" { } { { "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/me/altera/13.0sp1/quartus/linux/TimingClosureFloorplan.fld" "" "" { rtl~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/mnt/hgfs/vhdl/" { { 0 { 0 ""} 0 710 9224 9983 0} } } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1388350922718 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "AD_DA:AD_DA_Inst\|Mux10~1 Global clock " "Automatically promoted signal \"AD_DA:AD_DA_Inst\|Mux10~1\" to use Global clock" { } { { "AD_DA.vhd" "" { Text "/mnt/hgfs/vhdl/AD_DA.vhd" 43 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1388350922724 ""} { "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1388350922725 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1388350922753 ""} { "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1388350922864 ""} { "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1388350922867 ""} { "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1388350923010 ""} { "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1388350923012 ""} { "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1388350923012 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1388350923012 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1388350923136 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1388350923355 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1388350923708 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1388350923747 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1388350924710 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1388350924711 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1388350924816 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "/mnt/hgfs/vhdl/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1388350925193 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1388350925193 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1388350925646 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1388350925649 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1388350925649 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.39 " "Total time spent on timing analysis during the Fitter is 0.39 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1388350925675 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1388350925682 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/mnt/hgfs/vhdl/output_files/sk610-delay.fit.smsg " "Generated suppressed messages file /mnt/hgfs/vhdl/output_files/sk610-delay.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1388350925994 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "377 " "Peak virtual memory: 377 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1388350926102 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 29 22:02:06 2013 " "Processing ended: Sun Dec 29 22:02:06 2013" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1388350926102 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1388350926102 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1388350926102 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1388350926102 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1388350929473 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1388350929476 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 29 22:02:09 2013 " "Processing started: Sun Dec 29 22:02:09 2013" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1388350929476 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1388350929476 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay " "Command: quartus_asm --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1388350929477 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1388350930127 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1388350930184 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "309 " "Peak virtual memory: 309 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1388350930511 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 29 22:02:10 2013 " "Processing ended: Sun Dec 29 22:02:10 2013" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1388350930511 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1388350930511 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1388350930511 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1388350930511 ""} { "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1388350930705 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1388350933217 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1388350933219 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 29 22:02:12 2013 " "Processing started: Sun Dec 29 22:02:12 2013" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1388350933219 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1388350933219 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta sk610-delay -c sk610-delay " "Command: quartus_sta sk610-delay -c sk610-delay" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1388350933220 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1388350933322 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1388350933622 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1388350933789 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1388350933789 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1388350933960 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1388350934619 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES" "17 " "TimeQuest Timing Analyzer is analyzing 17 combinational loops as latches." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Quartus II" 0 -1 1388350934770 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "sk610-delay.sdc " "Synopsys Design Constraints File file not found: 'sk610-delay.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1388350934797 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1388350934798 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name Ram_Control:Ram_Control_Inst\|ram_state.activate Ram_Control:Ram_Control_Inst\|ram_state.activate " "create_clock -period 1.000 -name Ram_Control:Ram_Control_Inst\|ram_state.activate Ram_Control:Ram_Control_Inst\|ram_state.activate" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934809 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name Clk Clk " "create_clock -period 1.000 -name Clk Clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934809 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name V_Sync V_Sync " "create_clock -period 1.000 -name V_Sync V_Sync" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934809 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934809 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1388350934818 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1388350934862 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -7.396 " "Worst-case setup slack is -7.396" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934873 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934873 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.396 -544.256 Clk " " -7.396 -544.256 Clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934873 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.974 -158.291 Ram_Control:Ram_Control_Inst\|ram_state.activate " " -5.974 -158.291 Ram_Control:Ram_Control_Inst\|ram_state.activate " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934873 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.470 -22.073 V_Sync " " -3.470 -22.073 V_Sync " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934873 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1388350934873 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -3.834 " "Worst-case hold slack is -3.834" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934877 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934877 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.834 -31.201 Ram_Control:Ram_Control_Inst\|ram_state.activate " " -3.834 -31.201 Ram_Control:Ram_Control_Inst\|ram_state.activate " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934877 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.532 -12.848 Clk " " -1.532 -12.848 Clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934877 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.668 0.000 V_Sync " " 1.668 0.000 V_Sync " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934877 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1388350934877 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.925 " "Worst-case recovery slack is -6.925" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.925 -55.400 V_Sync " " -6.925 -55.400 V_Sync " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934890 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1388350934890 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 5.993 " "Worst-case removal slack is 5.993" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.993 0.000 V_Sync " " 5.993 0.000 V_Sync " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934901 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1388350934901 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934911 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934911 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 Clk " " -2.289 -2.289 Clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934911 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 V_Sync " " -2.289 -2.289 V_Sync " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934911 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.144 -125.626 Ram_Control:Ram_Control_Inst\|ram_state.activate " " -1.144 -125.626 Ram_Control:Ram_Control_Inst\|ram_state.activate " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1388350934911 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1388350934911 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1388350935098 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1388350935127 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1388350935128 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1388350935251 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 29 22:02:15 2013 " "Processing ended: Sun Dec 29 22:02:15 2013" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1388350935251 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1388350935251 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1388350935251 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1388350935251 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1388350939283 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1388350939286 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 29 22:02:18 2013 " "Processing started: Sun Dec 29 22:02:18 2013" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1388350939286 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1388350939286 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay " "Command: quartus_eda --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1388350939287 ""} { "Info" "IWSC_DONE_HDL_SDO_GENERATION" "sk610-delay.vho sk610-delay_vhd.sdo /mnt/hgfs/vhdl/simulation/modelsim/ simulation " "Generated files \"sk610-delay.vho\" and \"sk610-delay_vhd.sdo\" in directory \"/mnt/hgfs/vhdl/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204018 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "Quartus II" 0 -1 1388350940070 ""} { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "307 " "Peak virtual memory: 307 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1388350940199 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 29 22:02:20 2013 " "Processing ended: Sun Dec 29 22:02:20 2013" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1388350940199 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1388350940199 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1388350940199 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1388350940199 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 25 s " "Quartus II Full Compilation was successful. 0 errors, 25 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1388350940447 ""}