Flow report for sk610-delay
Sun Dec 29 22:02:20 2013
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log
  8. Flow Messages
  9. Flow Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Flow Summary                                                                ;
+---------------------------+-------------------------------------------------+
; Flow Status               ; Successful - Sun Dec 29 22:02:20 2013           ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name             ; sk610-delay                                     ;
; Top-level Entity Name     ; Top                                             ;
; Family                    ; MAX II                                          ;
; Device                    ; EPM240T100C5                                    ;
; Timing Models             ; Final                                           ;
; Total logic elements      ; 211 / 240 ( 88 % )                              ;
; Total pins                ; 58 / 80 ( 73 % )                                ;
; Total virtual pins        ; 0                                               ;
; UFM blocks                ; 0 / 1 ( 0 % )                                   ;
+---------------------------+-------------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 12/29/2013 22:01:54 ;
; Main task         ; Compilation         ;
; Revision Name     ; sk610-delay         ;
+-------------------+---------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                   ;
+---------------------------------------+-----------------------------+---------------+-------------+----------------+
; Assignment Name                       ; Value                       ; Default Value ; Entity Name ; Section Id     ;
+---------------------------------------+-----------------------------+---------------+-------------+----------------+
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP   ; On                          ; Off           ; --          ; --             ;
; AUTO_SHIFT_REGISTER_RECOGNITION       ; Always                      ; Auto          ; --          ; --             ;
; COMPILER_SIGNATURE_ID                 ; 52238391465.138835091414744 ; --            ; --          ; --             ;
; EDA_DESIGN_INSTANCE_NAME              ; NA                          ; --            ; --          ; Top_vhd_tst    ;
; EDA_NATIVELINK_SIMULATION_TEST_BENCH  ; Top_vhd_tst                 ; --            ; --          ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT                ; Vhdl                        ; --            ; --          ; eda_simulation ;
; EDA_SIMULATION_TOOL                   ; ModelSim-Altera (VHDL)      ; <None>        ; --          ; --             ;
; EDA_TEST_BENCH_ENABLE_STATUS          ; TEST_BENCH_MODE             ; --            ; --          ; eda_simulation ;
; EDA_TEST_BENCH_FILE                   ; Testbench.vhd               ; --            ; --          ; Top_vhd_tst    ;
; EDA_TEST_BENCH_MODULE_NAME            ; Top_vhd_tst                 ; --            ; --          ; Top_vhd_tst    ;
; EDA_TEST_BENCH_NAME                   ; Top_vhd_tst                 ; --            ; --          ; eda_simulation ;
; EDA_TEST_BENCH_RUN_SIM_FOR            ; 2 ms                        ; --            ; --          ; Top_vhd_tst    ;
; MAXII_OPTIMIZATION_TECHNIQUE          ; Area                        ; Balanced      ; --          ; --             ;
; MAX_CORE_JUNCTION_TEMP                ; 85                          ; --            ; --          ; --             ;
; MIN_CORE_JUNCTION_TEMP                ; 0                           ; --            ; --          ; --             ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V                        ; --            ; --          ; --             ;
; POWER_PRESET_COOLING_SOLUTION         ; No Heat Sink With Still Air ; --            ; --          ; --             ;
; PROJECT_OUTPUT_DIRECTORY              ; output_files                ; --            ; --          ; --             ;
; SMART_RECOMPILE                       ; On                          ; Off           ; --          ; --             ;
; TOP_LEVEL_ENTITY                      ; Top                         ; sk610-delay   ; --          ; --             ;
+---------------------------------------+-----------------------------+---------------+-------------+----------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                             ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis      ; 00:00:04     ; 1.0                     ; 360 MB              ; 00:00:03                           ;
; Fitter                    ; 00:00:05     ; 1.0                     ; 377 MB              ; 00:00:04                           ;
; Assembler                 ; 00:00:01     ; 1.0                     ; 309 MB              ; 00:00:01                           ;
; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 286 MB              ; 00:00:02                           ;
; EDA Netlist Writer        ; 00:00:02     ; 1.0                     ; 297 MB              ; 00:00:01                           ;
; Total                     ; 00:00:15     ; --                      ; --                  ; 00:00:11                           ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+


+---------------------------------------------------------------------------------------------+
; Flow OS Summary                                                                             ;
+---------------------------+------------------+----------------+------------+----------------+
; Module Name               ; Machine Hostname ; OS Name        ; OS Version ; Processor type ;
+---------------------------+------------------+----------------+------------+----------------+
; Analysis & Synthesis      ; ubuntu           ; Ubuntu 12.04.3 ; 12         ; i686           ;
; Fitter                    ; ubuntu           ; Ubuntu 12.04.3 ; 12         ; i686           ;
; Assembler                 ; ubuntu           ; Ubuntu 12.04.3 ; 12         ; i686           ;
; TimeQuest Timing Analyzer ; ubuntu           ; Ubuntu 12.04.3 ; 12         ; i686           ;
; EDA Netlist Writer        ; ubuntu           ; Ubuntu 12.04.3 ; 12         ; i686           ;
+---------------------------+------------------+----------------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off sk610-delay -c sk610-delay
quartus_fit --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay
quartus_asm --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay
quartus_sta sk610-delay -c sk610-delay
quartus_eda --read_settings_files=off --write_settings_files=off sk610-delay -c sk610-delay



