Analysis & Synthesis report for sk610-delay
Sun Dec 29 22:01:57 2013
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |Top|Ram_Control:Ram_Control_Inst|ram_next_state
  8. State Machine - |Top|Ram_Control:Ram_Control_Inst|ram_state
  9. User-Specified and Inferred Latches
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Port Connectivity Checks: "RX_TX:RX_TX_Inst"
 15. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Dec 29 22:01:57 2013           ;
; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name               ; sk610-delay                                     ;
; Top-level Entity Name       ; Top                                             ;
; Family                      ; MAX II                                          ;
; Total logic elements        ; 225                                             ;
; Total pins                  ; 58                                              ;
; Total virtual pins          ; 0                                               ;
; UFM blocks                  ; 0 / 1 ( 0 % )                                   ;
+-----------------------------+-------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EPM240T100C5       ;                    ;
; Top-level entity name                                                      ; Top                ; sk610-delay        ;
; Family name                                                                ; MAX II             ; Cyclone IV GX      ;
; Use smart compilation                                                      ; On                 ; Off                ;
; Optimization Technique                                                     ; Area               ; Balanced           ;
; Perform WYSIWYG Primitive Resynthesis                                      ; On                 ; Off                ;
; Auto Shift Register Replacement                                            ; Always             ; Auto               ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path       ; Library ;
+----------------------------------+-----------------+-----------------+------------------------------------+---------+
; RX_TX.vhd                        ; yes             ; User VHDL File  ; /mnt/hgfs/vhdl/RX_TX.vhd           ;         ;
; Address_Counter.vhd              ; yes             ; User VHDL File  ; /mnt/hgfs/vhdl/Address_Counter.vhd ;         ;
; Ram_Control.vhd                  ; yes             ; User VHDL File  ; /mnt/hgfs/vhdl/Ram_Control.vhd     ;         ;
; AD_DA.vhd                        ; yes             ; User VHDL File  ; /mnt/hgfs/vhdl/AD_DA.vhd           ;         ;
; Top.vhd                          ; yes             ; User VHDL File  ; /mnt/hgfs/vhdl/Top.vhd             ;         ;
+----------------------------------+-----------------+-----------------+------------------------------------+---------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 225   ;
;     -- Combinational with no register       ; 81    ;
;     -- Register only                        ; 59    ;
;     -- Combinational with a register        ; 85    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 35    ;
;     -- 3 input functions                    ; 63    ;
;     -- 2 input functions                    ; 63    ;
;     -- 1 input functions                    ; 5     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 176   ;
;     -- arithmetic mode                      ; 49    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 34    ;
;     -- asynchronous clear/load mode         ; 94    ;
;                                             ;       ;
; Total registers                             ; 144   ;
; Total logic cells in carry chains           ; 53    ;
; I/O pins                                    ; 58    ;
; Maximum fan-out node                        ; Clk   ;
; Maximum fan-out                             ; 110   ;
; Total fan-out                               ; 921   ;
; Average fan-out                             ; 3.25  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                       ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------+--------------+
; Compilation Hierarchy Node                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                       ; Library Name ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------+--------------+
; |Top                                      ; 225 (3)     ; 144          ; 0          ; 58   ; 0            ; 81 (1)       ; 59 (0)            ; 85 (2)           ; 53 (0)          ; 0 (0)      ; |Top                                      ; work         ;
;    |AD_DA:AD_DA_Inst|                     ; 28 (28)     ; 0            ; 0          ; 0    ; 0            ; 28 (28)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Top|AD_DA:AD_DA_Inst                     ; work         ;
;    |Address_Counter:Address_Counter_Inst| ; 42 (42)     ; 33           ; 0          ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 33 (33)          ; 39 (39)         ; 0 (0)      ; |Top|Address_Counter:Address_Counter_Inst ; work         ;
;    |RX_TX:RX_TX_Inst|                     ; 26 (26)     ; 24           ; 0          ; 0    ; 0            ; 2 (2)        ; 24 (24)           ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Top|RX_TX:RX_TX_Inst                     ; work         ;
;    |Ram_Control:Ram_Control_Inst|         ; 126 (126)   ; 85           ; 0          ; 0    ; 0            ; 41 (41)      ; 35 (35)           ; 50 (50)          ; 14 (14)         ; 0 (0)      ; |Top|Ram_Control:Ram_Control_Inst         ; work         ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Top|Ram_Control:Ram_Control_Inst|ram_next_state                                                                                                                                                                                                                                                                              ;
+----------------------------------+--------------------+--------------------------+-----------------------------+--------------------------+-----------------------------+-------------------------+-------------------------+-----------------------------+--------------------------+----------------------------------+---------------------+
; Name                             ; ram_next_state.nop ; ram_next_state.ram_write ; ram_next_state.nop_dqm_down ; ram_next_state.toggle_OE ; ram_next_state.ram_get_data ; ram_next_state.ram_read ; ram_next_state.activate ; ram_next_state.auto_refresh ; ram_next_state.precharge ; ram_next_state.set_mode_register ; ram_next_state.init ;
+----------------------------------+--------------------+--------------------------+-----------------------------+--------------------------+-----------------------------+-------------------------+-------------------------+-----------------------------+--------------------------+----------------------------------+---------------------+
; ram_next_state.init              ; 0                  ; 0                        ; 0                           ; 0                        ; 0                           ; 0                       ; 0                       ; 0                           ; 0                        ; 0                                ; 0                   ;
; ram_next_state.set_mode_register ; 0                  ; 0                        ; 0                           ; 0                        ; 0                           ; 0                       ; 0                       ; 0                           ; 0                        ; 1                                ; 1                   ;
; ram_next_state.precharge         ; 0                  ; 0                        ; 0                           ; 0                        ; 0                           ; 0                       ; 0                       ; 0                           ; 1                        ; 0                                ; 1                   ;
; ram_next_state.auto_refresh      ; 0                  ; 0                        ; 0                           ; 0                        ; 0                           ; 0                       ; 0                       ; 1                           ; 0                        ; 0                                ; 1                   ;
; ram_next_state.activate          ; 0                  ; 0                        ; 0                           ; 0                        ; 0                           ; 0                       ; 1                       ; 0                           ; 0                        ; 0                                ; 1                   ;
; ram_next_state.ram_read          ; 0                  ; 0                        ; 0                           ; 0                        ; 0                           ; 1                       ; 0                       ; 0                           ; 0                        ; 0                                ; 1                   ;
; ram_next_state.ram_get_data      ; 0                  ; 0                        ; 0                           ; 0                        ; 1                           ; 0                       ; 0                       ; 0                           ; 0                        ; 0                                ; 1                   ;
; ram_next_state.toggle_OE         ; 0                  ; 0                        ; 0                           ; 1                        ; 0                           ; 0                       ; 0                       ; 0                           ; 0                        ; 0                                ; 1                   ;
; ram_next_state.nop_dqm_down      ; 0                  ; 0                        ; 1                           ; 0                        ; 0                           ; 0                       ; 0                       ; 0                           ; 0                        ; 0                                ; 1                   ;
; ram_next_state.ram_write         ; 0                  ; 1                        ; 0                           ; 0                        ; 0                           ; 0                       ; 0                       ; 0                           ; 0                        ; 0                                ; 1                   ;
; ram_next_state.nop               ; 1                  ; 0                        ; 0                           ; 0                        ; 0                           ; 0                       ; 0                       ; 0                           ; 0                        ; 0                                ; 1                   ;
+----------------------------------+--------------------+--------------------------+-----------------------------+--------------------------+-----------------------------+-------------------------+-------------------------+-----------------------------+--------------------------+----------------------------------+---------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Top|Ram_Control:Ram_Control_Inst|ram_state                                                                                                                                                                                                                       ;
+-----------------------------+---------------+---------------------+------------------------+---------------------+------------------------+--------------------+--------------------+------------------------+---------------------+-----------------------------+----------------+
; Name                        ; ram_state.nop ; ram_state.ram_write ; ram_state.nop_dqm_down ; ram_state.toggle_OE ; ram_state.ram_get_data ; ram_state.ram_read ; ram_state.activate ; ram_state.auto_refresh ; ram_state.precharge ; ram_state.set_mode_register ; ram_state.init ;
+-----------------------------+---------------+---------------------+------------------------+---------------------+------------------------+--------------------+--------------------+------------------------+---------------------+-----------------------------+----------------+
; ram_state.init              ; 0             ; 0                   ; 0                      ; 0                   ; 0                      ; 0                  ; 0                  ; 0                      ; 0                   ; 0                           ; 0              ;
; ram_state.set_mode_register ; 0             ; 0                   ; 0                      ; 0                   ; 0                      ; 0                  ; 0                  ; 0                      ; 0                   ; 1                           ; 1              ;
; ram_state.precharge         ; 0             ; 0                   ; 0                      ; 0                   ; 0                      ; 0                  ; 0                  ; 0                      ; 1                   ; 0                           ; 1              ;
; ram_state.auto_refresh      ; 0             ; 0                   ; 0                      ; 0                   ; 0                      ; 0                  ; 0                  ; 1                      ; 0                   ; 0                           ; 1              ;
; ram_state.activate          ; 0             ; 0                   ; 0                      ; 0                   ; 0                      ; 0                  ; 1                  ; 0                      ; 0                   ; 0                           ; 1              ;
; ram_state.ram_read          ; 0             ; 0                   ; 0                      ; 0                   ; 0                      ; 1                  ; 0                  ; 0                      ; 0                   ; 0                           ; 1              ;
; ram_state.ram_get_data      ; 0             ; 0                   ; 0                      ; 0                   ; 1                      ; 0                  ; 0                  ; 0                      ; 0                   ; 0                           ; 1              ;
; ram_state.toggle_OE         ; 0             ; 0                   ; 0                      ; 1                   ; 0                      ; 0                  ; 0                  ; 0                      ; 0                   ; 0                           ; 1              ;
; ram_state.nop_dqm_down      ; 0             ; 0                   ; 1                      ; 0                   ; 0                      ; 0                  ; 0                  ; 0                      ; 0                   ; 0                           ; 1              ;
; ram_state.ram_write         ; 0             ; 1                   ; 0                      ; 0                   ; 0                      ; 0                  ; 0                  ; 0                      ; 0                   ; 0                           ; 1              ;
; ram_state.nop               ; 1             ; 0                   ; 0                      ; 0                   ; 0                      ; 0                  ; 0                  ; 0                      ; 0                   ; 0                           ; 1              ;
+-----------------------------+---------------+---------------------+------------------------+---------------------+------------------------+--------------------+--------------------+------------------------+---------------------+-----------------------------+----------------+


+-------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                   ;
+-----------------------------------------------------+------------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal    ; Free of Timing Hazards ;
+-----------------------------------------------------+------------------------+------------------------+
; AD_DA:AD_DA_Inst|AD_Clk                             ; AD_DA:AD_DA_Inst|Mux1  ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Clk                             ; AD_DA:AD_DA_Inst|Mux1  ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[0]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[1]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[2]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[3]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[4]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[5]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[6]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|DA_Out[7]                          ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[0]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[1]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[2]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[3]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[4]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[5]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[6]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; AD_DA:AD_DA_Inst|ad_data[7]                         ; AD_DA:AD_DA_Inst|Mux10 ; yes                    ;
; Number of user-specified and inferred latches = 18  ;                        ;                        ;
+-----------------------------------------------------+------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                     ;
+----------------------------------------------------------+-------------------------------------------------------------+
; Register name                                            ; Reason for Removal                                          ;
+----------------------------------------------------------+-------------------------------------------------------------+
; Ram_Control:Ram_Control_Inst|ram_next_state.nop_dqm_down ; Merged with Ram_Control:Ram_Control_Inst|ram_next_state.nop ;
; Ram_Control:Ram_Control_Inst|ram_next_state.ram_write    ; Merged with Ram_Control:Ram_Control_Inst|ram_next_state.nop ;
; Ram_Control:Ram_Control_Inst|ram_next_state.toggle_OE    ; Merged with Ram_Control:Ram_Control_Inst|ram_next_state.nop ;
; Ram_Control:Ram_Control_Inst|ram_next_state.nop          ; Stuck at GND due to stuck port data_in                      ;
; Total Number of Removed Registers = 4                    ;                                                             ;
+----------------------------------------------------------+-------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 144   ;
; Number of registers using Synchronous Clear  ; 24    ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 94    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 72    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; we                                     ; 2       ;
; Ram_Control:Ram_Control_Inst|OEn       ; 9       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+
; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; Yes        ; |Top|Ram_Control:Ram_Control_Inst|address_temp[11]         ;
; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |Top|Ram_Control:Ram_Control_Inst|ram_nops[7]              ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; No         ; |Top|Ram_Control:Ram_Control_Inst|ram_next_state.toggle_OE ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; No         ; |Top|Ram_Control:Ram_Control_Inst|ram_state                ;
; 1:1                ; 8 bits    ; 0 LEs         ; 0 LEs                ; 0 LEs                  ; No         ; |Top|AD_DA:AD_DA_Inst|Mux15                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "RX_TX:RX_TX_Inst"                                                                     ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; Port   ; Type   ; Severity ; Details                                                                             ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; strobe ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Dec 29 22:01:53 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sk610-delay -c sk610-delay
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file RX_TX.vhd
    Info (12022): Found design unit 1: RX_TX-RX_TX_arch
    Info (12023): Found entity 1: RX_TX
Info (12021): Found 2 design units, including 1 entities, in source file Address_Counter.vhd
    Info (12022): Found design unit 1: Address_Counter-Address_Counter_arch
    Info (12023): Found entity 1: Address_Counter
Info (12021): Found 2 design units, including 1 entities, in source file Ram_Control.vhd
    Info (12022): Found design unit 1: Ram_Control-Ram_Control_arch
    Info (12023): Found entity 1: Ram_Control
Info (12021): Found 2 design units, including 1 entities, in source file AD_DA.vhd
    Info (12022): Found design unit 1: AD_DA-AD_DA_Arch
    Info (12023): Found entity 1: AD_DA
Info (12021): Found 2 design units, including 1 entities, in source file Top.vhd
    Info (12022): Found design unit 1: Top-Top_Arch
    Info (12023): Found entity 1: Top
Info (12127): Elaborating entity "Top" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at Top.vhd(122): object "load_max" assigned a value but never read
Info (12128): Elaborating entity "Address_Counter" for hierarchy "Address_Counter:Address_Counter_Inst"
Info (12128): Elaborating entity "AD_DA" for hierarchy "AD_DA:AD_DA_Inst"
Warning (10492): VHDL Process Statement warning at AD_DA.vhd(45): signal "AD_Input" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at AD_DA.vhd(46): signal "da_data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable "ad_data", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable "DA_Out", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable "DA_Clk", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at AD_DA.vhd(41): inferring latch(es) for signal or variable "AD_Clk", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "AD_Clk" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Clk" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[0]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[1]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[2]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[3]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[4]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[5]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[6]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "DA_Out[7]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[0]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[1]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[2]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[3]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[4]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[5]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[6]" at AD_DA.vhd(41)
Info (10041): Inferred latch for "ad_data[7]" at AD_DA.vhd(41)
Info (12128): Elaborating entity "Ram_Control" for hierarchy "Ram_Control:Ram_Control_Inst"
Warning (10492): VHDL Process Statement warning at Ram_Control.vhd(264): signal "write_buf" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info (12128): Elaborating entity "RX_TX" for hierarchy "RX_TX:RX_TX_Inst"
Warning (10541): VHDL Signal Declaration warning at RX_TX.vhd(19): used implicit default value for signal "MISO" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (19016): Clock multiplexers are found and protected
    Warning (19017): Found clock multiplexer Address_Counter:Address_Counter_Inst|Mux0
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
Info (13025): Duplicate LATCH primitives merged into single LATCH primitive
    Info (13026): Duplicate LATCH primitive "AD_DA:AD_DA_Inst|DA_Clk" merged with LATCH primitive "AD_DA:AD_DA_Inst|AD_Clk"
Warning (13012): Latch AD_DA:AD_DA_Inst|AD_Clk has unsafe behavior
    Warning (13013): Ports D and ENA on the latch are fed by the same signal Ram_Control:Ram_Control_Inst|ram_state.precharge
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "Led2" is stuck at GND
    Warning (13410): Pin "MISO" is stuck at GND
Info (18000): Registers with preset signals will power-up high
Info (21057): Implemented 283 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 16 input pins
    Info (21059): Implemented 34 output pins
    Info (21060): Implemented 8 bidirectional pins
    Info (21061): Implemented 225 logic cells
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 17 warnings
    Info: Peak virtual memory: 360 megabytes
    Info: Processing ended: Sun Dec 29 22:01:57 2013
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:03


