TimeQuest Timing Analyzer report for sk610-delay
Sun Dec 29 22:02:15 2013
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Clocks
  4. Fmax Summary
  5. Setup Summary
  6. Hold Summary
  7. Recovery Summary
  8. Removal Summary
  9. Minimum Pulse Width Summary
 10. Setup: 'Clk'
 11. Setup: 'Ram_Control:Ram_Control_Inst|ram_state.activate'
 12. Setup: 'V_Sync'
 13. Hold: 'Ram_Control:Ram_Control_Inst|ram_state.activate'
 14. Hold: 'Clk'
 15. Hold: 'V_Sync'
 16. Recovery: 'V_Sync'
 17. Removal: 'V_Sync'
 18. Minimum Pulse Width: 'Clk'
 19. Minimum Pulse Width: 'V_Sync'
 20. Minimum Pulse Width: 'Ram_Control:Ram_Control_Inst|ram_state.activate'
 21. Setup Times
 22. Hold Times
 23. Clock to Output Times
 24. Minimum Clock to Output Times
 25. Propagation Delay
 26. Minimum Propagation Delay
 27. Output Enable Times
 28. Minimum Output Enable Times
 29. Output Disable Times
 30. Minimum Output Disable Times
 31. Setup Transfers
 32. Hold Transfers
 33. Recovery Transfers
 34. Removal Transfers
 35. Report TCCS
 36. Report RSKM
 37. Unconstrained Paths
 38. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; sk610-delay                                                       ;
; Device Family      ; MAX II                                                            ;
; Device Name        ; EPM240T100C5                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Slow Model                                                        ;
; Rise/Fall Delays   ; Unavailable                                                       ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                           ;
+-------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------+
; Clock Name                                      ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                             ;
+-------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------+
; Clk                                             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { Clk }                                             ;
; Ram_Control:Ram_Control_Inst|ram_state.activate ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { Ram_Control:Ram_Control_Inst|ram_state.activate } ;
; V_Sync                                          ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { V_Sync }                                          ;
+-------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------+
; Fmax Summary                                                                          ;
+------------+-----------------+-------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                      ; Note ;
+------------+-----------------+-------------------------------------------------+------+
; 119.82 MHz ; 119.82 MHz      ; Clk                                             ;      ;
; 143.39 MHz ; 143.39 MHz      ; Ram_Control:Ram_Control_Inst|ram_state.activate ;      ;
; 223.71 MHz ; 223.71 MHz      ; V_Sync                                          ;      ;
+------------+-----------------+-------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------+
; Setup Summary                                                            ;
+-------------------------------------------------+--------+---------------+
; Clock                                           ; Slack  ; End Point TNS ;
+-------------------------------------------------+--------+---------------+
; Clk                                             ; -7.396 ; -544.256      ;
; Ram_Control:Ram_Control_Inst|ram_state.activate ; -5.974 ; -158.291      ;
; V_Sync                                          ; -3.470 ; -22.073       ;
+-------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------+
; Hold Summary                                                             ;
+-------------------------------------------------+--------+---------------+
; Clock                                           ; Slack  ; End Point TNS ;
+-------------------------------------------------+--------+---------------+
; Ram_Control:Ram_Control_Inst|ram_state.activate ; -3.834 ; -31.201       ;
; Clk                                             ; -1.532 ; -12.848       ;
; V_Sync                                          ; 1.668  ; 0.000         ;
+-------------------------------------------------+--------+---------------+


+---------------------------------+
; Recovery Summary                ;
+--------+--------+---------------+
; Clock  ; Slack  ; End Point TNS ;
+--------+--------+---------------+
; V_Sync ; -6.925 ; -55.400       ;
+--------+--------+---------------+


+--------------------------------+
; Removal Summary                ;
+--------+-------+---------------+
; Clock  ; Slack ; End Point TNS ;
+--------+-------+---------------+
; V_Sync ; 5.993 ; 0.000         ;
+--------+-------+---------------+


+--------------------------------------------------------------------------+
; Minimum Pulse Width Summary                                              ;
+-------------------------------------------------+--------+---------------+
; Clock                                           ; Slack  ; End Point TNS ;
+-------------------------------------------------+--------+---------------+
; Clk                                             ; -2.289 ; -2.289        ;
; V_Sync                                          ; -2.289 ; -2.289        ;
; Ram_Control:Ram_Control_Inst|ram_state.activate ; -1.144 ; -125.626      ;
+-------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'Clk'                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                  ; Launch Clock                                    ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; -7.396 ; Address_Counter:Address_Counter_Inst|counter_count[11] ; Ram_Control:Ram_Control_Inst|address_buf[11]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 3.448      ;
; -7.360 ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|address_buf[22]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 3.412      ;
; -7.346 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 8.013      ;
; -7.346 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 8.013      ;
; -7.346 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 8.013      ;
; -7.340 ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|address_buf[21]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 3.392      ;
; -7.181 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.848      ;
; -7.181 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.848      ;
; -7.181 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.848      ;
; -7.175 ; Address_Counter:Address_Counter_Inst|counter_count[16] ; Ram_Control:Ram_Control_Inst|address_buf[16]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 3.227      ;
; -7.154 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.821      ;
; -7.154 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.821      ;
; -7.154 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.821      ;
; -7.073 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.740      ;
; -7.073 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.740      ;
; -7.073 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.740      ;
; -6.968 ; Ram_Control:Ram_Control_Inst|ram_nops[9]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.635      ;
; -6.968 ; Ram_Control:Ram_Control_Inst|ram_nops[9]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.635      ;
; -6.968 ; Ram_Control:Ram_Control_Inst|ram_nops[9]               ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.635      ;
; -6.920 ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|address_buf[19]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.972      ;
; -6.914 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[6]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.581      ;
; -6.914 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[4]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.581      ;
; -6.897 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Ram_Control:Ram_Control_Inst|address_buf[13]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.949      ;
; -6.883 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[0]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.550      ;
; -6.866 ; Ram_Control:Ram_Control_Inst|ram_nops[1]               ; Ram_Control:Ram_Control_Inst|ram_nops[1]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.533      ;
; -6.853 ; Ram_Control:Ram_Control_Inst|ram_nops[1]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.520      ;
; -6.853 ; Ram_Control:Ram_Control_Inst|ram_nops[1]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.520      ;
; -6.853 ; Ram_Control:Ram_Control_Inst|ram_nops[1]               ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.520      ;
; -6.830 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[2]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.497      ;
; -6.824 ; Ram_Control:Ram_Control_Inst|ram_nops[11]              ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.491      ;
; -6.824 ; Ram_Control:Ram_Control_Inst|ram_nops[11]              ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.491      ;
; -6.824 ; Ram_Control:Ram_Control_Inst|ram_nops[11]              ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.491      ;
; -6.789 ; Ram_Control:Ram_Control_Inst|ram_nops[10]              ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.456      ;
; -6.789 ; Ram_Control:Ram_Control_Inst|ram_nops[10]              ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.456      ;
; -6.789 ; Ram_Control:Ram_Control_Inst|ram_nops[10]              ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.456      ;
; -6.765 ; Ram_Control:Ram_Control_Inst|ram_nops[7]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.432      ;
; -6.765 ; Ram_Control:Ram_Control_Inst|ram_nops[7]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.432      ;
; -6.765 ; Ram_Control:Ram_Control_Inst|ram_nops[7]               ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.432      ;
; -6.763 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_state.precharge         ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.430      ;
; -6.762 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_state.set_mode_register ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.429      ;
; -6.749 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[1]              ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.416      ;
; -6.749 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[2]              ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.416      ;
; -6.749 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[6]              ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.416      ;
; -6.749 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[6]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.416      ;
; -6.749 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[4]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.416      ;
; -6.722 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_nops[6]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.389      ;
; -6.722 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_nops[4]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.389      ;
; -6.721 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_state.auto_refresh      ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.388      ;
; -6.671 ; Address_Counter:Address_Counter_Inst|counter_count[15] ; Ram_Control:Ram_Control_Inst|address_buf[15]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.723      ;
; -6.661 ; Ram_Control:Ram_Control_Inst|ram_state.ram_read        ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.328      ;
; -6.661 ; Ram_Control:Ram_Control_Inst|ram_state.ram_read        ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.328      ;
; -6.661 ; Ram_Control:Ram_Control_Inst|ram_state.ram_read        ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.328      ;
; -6.659 ; Address_Counter:Address_Counter_Inst|counter_count[9]  ; Ram_Control:Ram_Control_Inst|address_buf[9]              ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.711      ;
; -6.643 ; Address_Counter:Address_Counter_Inst|counter_count[10] ; Ram_Control:Ram_Control_Inst|address_buf[10]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.695      ;
; -6.641 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_nops[6]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.308      ;
; -6.641 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_nops[4]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.308      ;
; -6.613 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Ram_Control:Ram_Control_Inst|address_buf[12]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.665      ;
; -6.613 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Ram_Control:Ram_Control_Inst|address_buf[7]              ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.665      ;
; -6.609 ; Ram_Control:Ram_Control_Inst|ram_nops[13]              ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.276      ;
; -6.609 ; Ram_Control:Ram_Control_Inst|ram_nops[13]              ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.276      ;
; -6.609 ; Ram_Control:Ram_Control_Inst|ram_nops[13]              ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.276      ;
; -6.577 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[1]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.244      ;
; -6.572 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[5]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.239      ;
; -6.571 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_state.precharge         ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.238      ;
; -6.570 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_state.set_mode_register ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.237      ;
; -6.569 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_state.nop               ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.236      ;
; -6.568 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data      ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.235      ;
; -6.567 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_state.ram_read          ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.234      ;
; -6.565 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_nops[0]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.232      ;
; -6.560 ; Ram_Control:Ram_Control_Inst|ram_nops[8]               ; Ram_Control:Ram_Control_Inst|ram_state.activate          ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.227      ;
; -6.555 ; Ram_Control:Ram_Control_Inst|ram_nops[4]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.222      ;
; -6.546 ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|address_buf[18]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.598      ;
; -6.545 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[17]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.212      ;
; -6.545 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[20]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.212      ;
; -6.545 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[23]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.212      ;
; -6.536 ; Ram_Control:Ram_Control_Inst|ram_nops[9]               ; Ram_Control:Ram_Control_Inst|ram_nops[6]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.203      ;
; -6.536 ; Ram_Control:Ram_Control_Inst|ram_nops[9]               ; Ram_Control:Ram_Control_Inst|ram_nops[4]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.203      ;
; -6.529 ; Ram_Control:Ram_Control_Inst|ram_nops[0]               ; Ram_Control:Ram_Control_Inst|ram_state.auto_refresh      ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.196      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[13]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[16]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[7]              ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[19]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[10]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[21]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[11]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.528 ; Ram_Control:Ram_Control_Inst|ram_state.precharge       ; Ram_Control:Ram_Control_Inst|address_buf[22]             ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.195      ;
; -6.521 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Ram_Control:Ram_Control_Inst|address_buf[8]              ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.573      ;
; -6.504 ; Ram_Control:Ram_Control_Inst|ram_nops[5]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.171      ;
; -6.504 ; Ram_Control:Ram_Control_Inst|ram_nops[5]               ; Ram_Control:Ram_Control_Inst|ram_nops[12]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.171      ;
; -6.504 ; Ram_Control:Ram_Control_Inst|ram_nops[5]               ; Ram_Control:Ram_Control_Inst|ram_nops[7]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.171      ;
; -6.490 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_state.precharge         ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.157      ;
; -6.489 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_state.set_mode_register ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.156      ;
; -6.466 ; Address_Counter:Address_Counter_Inst|counter_count[14] ; Ram_Control:Ram_Control_Inst|address_buf[14]             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 1.000        ; -4.615     ; 2.518      ;
; -6.463 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data    ; Ram_Control:Ram_Control_Inst|ram_nops[8]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.130      ;
; -6.448 ; Ram_Control:Ram_Control_Inst|ram_nops[6]               ; Ram_Control:Ram_Control_Inst|ram_state.auto_refresh      ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.115      ;
; -6.421 ; Ram_Control:Ram_Control_Inst|ram_nops[1]               ; Ram_Control:Ram_Control_Inst|ram_nops[6]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.088      ;
; -6.421 ; Ram_Control:Ram_Control_Inst|ram_nops[1]               ; Ram_Control:Ram_Control_Inst|ram_nops[4]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.088      ;
; -6.392 ; Ram_Control:Ram_Control_Inst|ram_nops[4]               ; Ram_Control:Ram_Control_Inst|ram_nops[13]                ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.059      ;
; -6.392 ; Ram_Control:Ram_Control_Inst|ram_nops[11]              ; Ram_Control:Ram_Control_Inst|ram_nops[6]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.059      ;
; -6.392 ; Ram_Control:Ram_Control_Inst|ram_nops[11]              ; Ram_Control:Ram_Control_Inst|ram_nops[4]                 ; Clk                                             ; Clk         ; 1.000        ; 0.000      ; 7.059      ;
+--------+--------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'Ram_Control:Ram_Control_Inst|ram_state.activate'                                                                                                                                                                                                              ;
+--------+--------------------------------------------------------+--------------------------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+--------------------------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; -5.974 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.263      ;
; -5.974 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.263      ;
; -5.974 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.263      ;
; -5.974 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.263      ;
; -5.974 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.263      ;
; -5.961 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.250      ;
; -5.961 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.250      ;
; -5.840 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.129      ;
; -5.840 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.129      ;
; -5.840 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.129      ;
; -5.840 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.129      ;
; -5.840 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.129      ;
; -5.827 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.116      ;
; -5.827 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.116      ;
; -5.789 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.078      ;
; -5.789 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.078      ;
; -5.789 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.078      ;
; -5.789 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.078      ;
; -5.789 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.078      ;
; -5.776 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.065      ;
; -5.776 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 5.065      ;
; -5.656 ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.945      ;
; -5.656 ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.945      ;
; -5.656 ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.945      ;
; -5.656 ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.945      ;
; -5.656 ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.945      ;
; -5.643 ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.932      ;
; -5.643 ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.932      ;
; -5.578 ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.867      ;
; -5.578 ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.867      ;
; -5.578 ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.867      ;
; -5.578 ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.867      ;
; -5.578 ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.867      ;
; -5.565 ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.854      ;
; -5.565 ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.854      ;
; -5.469 ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.758      ;
; -5.469 ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.758      ;
; -5.469 ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.758      ;
; -5.469 ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.758      ;
; -5.469 ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.758      ;
; -5.456 ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.745      ;
; -5.456 ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.745      ;
; -5.379 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[11] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.668      ;
; -5.379 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.668      ;
; -5.379 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.668      ;
; -5.379 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[9]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.668      ;
; -5.379 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[10] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.668      ;
; -5.366 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.655      ;
; -5.366 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.655      ;
; -5.366 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[14] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.655      ;
; -5.366 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[15] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.655      ;
; -5.366 ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Address_Counter:Address_Counter_Inst|counter_count[16] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.655      ;
; -5.351 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.640      ;
; -5.351 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.640      ;
; -5.351 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.640      ;
; -5.351 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.640      ;
; -5.351 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.640      ;
; -5.339 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.628      ;
; -5.339 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.628      ;
; -5.339 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.628      ;
; -5.339 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.628      ;
; -5.339 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.628      ;
; -5.338 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.627      ;
; -5.338 ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.627      ;
; -5.326 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.615      ;
; -5.326 ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.615      ;
; -5.319 ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.608      ;
; -5.319 ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.608      ;
; -5.319 ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.608      ;
; -5.319 ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.608      ;
; -5.319 ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.608      ;
; -5.306 ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.595      ;
; -5.306 ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.595      ;
; -5.245 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[11] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.534      ;
; -5.245 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.534      ;
; -5.245 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.534      ;
; -5.245 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[9]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.534      ;
; -5.245 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[10] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.534      ;
; -5.232 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.521      ;
; -5.232 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.521      ;
; -5.232 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[14] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.521      ;
; -5.232 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[15] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.521      ;
; -5.232 ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Address_Counter:Address_Counter_Inst|counter_count[16] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.521      ;
; -5.229 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.518      ;
; -5.229 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.518      ;
; -5.229 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.518      ;
; -5.229 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.518      ;
; -5.229 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.518      ;
; -5.226 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.515      ;
; -5.226 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.515      ;
; -5.226 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.515      ;
; -5.226 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.515      ;
; -5.226 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.515      ;
; -5.216 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.505      ;
; -5.216 ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.505      ;
; -5.213 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.502      ;
; -5.213 ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.502      ;
; -5.194 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[11] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.483      ;
; -5.194 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.483      ;
; -5.194 ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.000        ; -1.378     ; 4.483      ;
+--------+--------------------------------------------------------+--------------------------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'V_Sync'                                                                                                                                                                          ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -3.470 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 4.137      ;
; -3.470 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 4.137      ;
; -3.470 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 4.137      ;
; -3.240 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.907      ;
; -3.240 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.907      ;
; -3.240 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.907      ;
; -3.208 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.875      ;
; -3.208 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.875      ;
; -3.208 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.875      ;
; -3.118 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.785      ;
; -3.118 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.785      ;
; -3.118 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.785      ;
; -3.046 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.713      ;
; -3.046 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.713      ;
; -3.046 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.713      ;
; -3.003 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.670      ;
; -2.880 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.547      ;
; -2.863 ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.530      ;
; -2.773 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.440      ;
; -2.757 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[2] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.424      ;
; -2.741 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.408      ;
; -2.741 ; Address_Counter:Address_Counter_Inst|frame_count[6] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.408      ;
; -2.740 ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.407      ;
; -2.651 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.318      ;
; -2.650 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.317      ;
; -2.528 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.195      ;
; -2.527 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[2] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 3.194      ;
; -2.187 ; Address_Counter:Address_Counter_Inst|frame_count[7] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.854      ;
; -1.801 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[1] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.468      ;
; -1.785 ; Address_Counter:Address_Counter_Inst|frame_count[6] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.452      ;
; -1.785 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.452      ;
; -1.785 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.452      ;
; -1.784 ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.451      ;
; -1.681 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[2] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.348      ;
; -1.680 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[1] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 2.347      ;
; -1.222 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[0] ; V_Sync       ; V_Sync      ; 1.000        ; 0.000      ; 1.889      ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'Ram_Control:Ram_Control_Inst|ram_state.activate'                                                                                                                                                                                                                 ;
+--------+----------------------------------------------------------+--------------------------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                ; To Node                                                ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------+--------------------------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; -3.834 ; Ram_Control:Ram_Control_Inst|Read_Data[2]                ; AD_DA:AD_DA_Inst|DA_Out[2]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.310      ; 1.476      ;
; -3.826 ; Ram_Control:Ram_Control_Inst|Read_Data[0]                ; AD_DA:AD_DA_Inst|DA_Out[0]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.302      ; 1.476      ;
; -3.826 ; Ram_Control:Ram_Control_Inst|Read_Data[1]                ; AD_DA:AD_DA_Inst|DA_Out[1]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.302      ; 1.476      ;
; -3.810 ; Ram_Control:Ram_Control_Inst|Read_Data[3]                ; AD_DA:AD_DA_Inst|DA_Out[3]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.286      ; 1.476      ;
; -3.810 ; Ram_Control:Ram_Control_Inst|Read_Data[4]                ; AD_DA:AD_DA_Inst|DA_Out[4]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.286      ; 1.476      ;
; -3.509 ; Ram_Control:Ram_Control_Inst|Read_Data[7]                ; AD_DA:AD_DA_Inst|DA_Out[7]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.214      ; 1.705      ;
; -3.405 ; Ram_Control:Ram_Control_Inst|Read_Data[6]                ; AD_DA:AD_DA_Inst|DA_Out[6]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.296      ; 1.891      ;
; -3.328 ; Ram_Control:Ram_Control_Inst|Read_Data[5]                ; AD_DA:AD_DA_Inst|DA_Out[5]                             ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 5.223      ; 1.895      ;
; -1.742 ; Ram_Control:Ram_Control_Inst|ram_state.ram_write         ; AD_DA:AD_DA_Inst|AD_Clk                                ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 4.223      ; 1.981      ;
; -1.343 ; Ram_Control:Ram_Control_Inst|ram_state.precharge         ; AD_DA:AD_DA_Inst|AD_Clk                                ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 4.223      ; 2.380      ;
; -1.217 ; Ram_Control:Ram_Control_Inst|ram_state.set_mode_register ; AD_DA:AD_DA_Inst|AD_Clk                                ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 4.223      ; 2.506      ;
; -0.771 ; Ram_Control:Ram_Control_Inst|ram_state.ram_read          ; AD_DA:AD_DA_Inst|AD_Clk                                ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 4.223      ; 2.952      ;
; -0.582 ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data      ; AD_DA:AD_DA_Inst|AD_Clk                                ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 4.223      ; 3.141      ;
; -0.226 ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[4]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.441      ; 2.715      ;
; -0.224 ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[3]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.441      ; 2.717      ;
; -0.111 ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_did_reset ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 3.594      ;
; -0.072 ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 4.764      ;
; 0.107  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 4.943      ;
; 0.164  ; AD_DA:AD_DA_Inst|ad_data[1]                              ; AD_DA:AD_DA_Inst|DA_Out[1]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.846      ; 1.010      ;
; 0.164  ; AD_DA:AD_DA_Inst|ad_data[4]                              ; AD_DA:AD_DA_Inst|DA_Out[4]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.846      ; 1.010      ;
; 0.172  ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[2]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.465      ; 3.137      ;
; 0.174  ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[6]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.451      ; 3.125      ;
; 0.184  ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[1]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.457      ; 3.141      ;
; 0.186  ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[0]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.457      ; 3.143      ;
; 0.293  ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[7]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.369      ; 3.162      ;
; 0.399  ; AD_DA:AD_DA_Inst|ad_data[0]                              ; AD_DA:AD_DA_Inst|DA_Out[0]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.840      ; 1.239      ;
; 0.399  ; AD_DA:AD_DA_Inst|ad_data[3]                              ; AD_DA:AD_DA_Inst|DA_Out[3]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.840      ; 1.239      ;
; 0.401  ; AD_DA:AD_DA_Inst|ad_data[7]                              ; AD_DA:AD_DA_Inst|DA_Out[7]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.838      ; 1.239      ;
; 0.477  ; bypass                                                   ; AD_DA:AD_DA_Inst|DA_Out[5]                             ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; -0.500       ; 3.378      ; 3.355      ;
; 0.574  ; AD_DA:AD_DA_Inst|ad_data[5]                              ; AD_DA:AD_DA_Inst|DA_Out[5]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.855      ; 1.429      ;
; 0.579  ; AD_DA:AD_DA_Inst|ad_data[6]                              ; AD_DA:AD_DA_Inst|DA_Out[6]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.846      ; 1.425      ;
; 0.608  ; AD_DA:AD_DA_Inst|ad_data[2]                              ; AD_DA:AD_DA_Inst|DA_Out[2]                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 0.846      ; 1.454      ;
; 0.640  ; RX_TX:RX_TX_Inst|Receive_Data[6]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.476      ;
; 0.666  ; RX_TX:RX_TX_Inst|Receive_Data[0]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.502      ;
; 0.669  ; Address_Counter:Address_Counter_Inst|counter_count[23]   ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.268      ;
; 0.730  ; Address_Counter:Address_Counter_Inst|counter_count[4]    ; Address_Counter:Address_Counter_Inst|counter_count[4]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.329      ;
; 0.738  ; Address_Counter:Address_Counter_Inst|counter_count[7]    ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.337      ;
; 0.739  ; Address_Counter:Address_Counter_Inst|counter_count[14]   ; Address_Counter:Address_Counter_Inst|counter_count[14] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.338      ;
; 0.739  ; Address_Counter:Address_Counter_Inst|counter_count[18]   ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.338      ;
; 0.739  ; Address_Counter:Address_Counter_Inst|counter_count[19]   ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.338      ;
; 0.748  ; Address_Counter:Address_Counter_Inst|counter_count[16]   ; Address_Counter:Address_Counter_Inst|counter_count[16] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.347      ;
; 0.748  ; Address_Counter:Address_Counter_Inst|counter_count[8]    ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.347      ;
; 0.748  ; Address_Counter:Address_Counter_Inst|counter_count[9]    ; Address_Counter:Address_Counter_Inst|counter_count[9]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.347      ;
; 0.750  ; Address_Counter:Address_Counter_Inst|counter_count[6]    ; Address_Counter:Address_Counter_Inst|counter_count[6]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.349      ;
; 0.843  ; Address_Counter:Address_Counter_Inst|counter_count[15]   ; Address_Counter:Address_Counter_Inst|counter_count[15] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.442      ;
; 0.843  ; Address_Counter:Address_Counter_Inst|counter_count[10]   ; Address_Counter:Address_Counter_Inst|counter_count[10] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.442      ;
; 0.851  ; Address_Counter:Address_Counter_Inst|counter_count[22]   ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.450      ;
; 0.852  ; Address_Counter:Address_Counter_Inst|counter_count[12]   ; Address_Counter:Address_Counter_Inst|counter_count[12] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.451      ;
; 0.853  ; Address_Counter:Address_Counter_Inst|counter_count[0]    ; Address_Counter:Address_Counter_Inst|counter_count[0]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.452      ;
; 0.853  ; Address_Counter:Address_Counter_Inst|counter_count[11]   ; Address_Counter:Address_Counter_Inst|counter_count[11] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.452      ;
; 0.853  ; Address_Counter:Address_Counter_Inst|counter_count[13]   ; Address_Counter:Address_Counter_Inst|counter_count[13] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.452      ;
; 0.853  ; Address_Counter:Address_Counter_Inst|counter_count[5]    ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.452      ;
; 0.853  ; Address_Counter:Address_Counter_Inst|counter_count[21]   ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.452      ;
; 0.869  ; Address_Counter:Address_Counter_Inst|counter_count[3]    ; Address_Counter:Address_Counter_Inst|counter_count[3]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.468      ;
; 0.880  ; Address_Counter:Address_Counter_Inst|counter_count[2]    ; Address_Counter:Address_Counter_Inst|counter_count[2]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.479      ;
; 0.882  ; Address_Counter:Address_Counter_Inst|counter_count[1]    ; Address_Counter:Address_Counter_Inst|counter_count[1]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.481      ;
; 1.033  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[17] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 4.738      ;
; 1.033  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[18] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 4.738      ;
; 1.033  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[19] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 4.738      ;
; 1.033  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[20] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 4.738      ;
; 1.033  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[21] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 4.738      ;
; 1.033  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[22] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 4.738      ;
; 1.033  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[23] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 4.738      ;
; 1.072  ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.908      ;
; 1.072  ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.908      ;
; 1.072  ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.908      ;
; 1.072  ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.908      ;
; 1.072  ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.908      ;
; 1.072  ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.908      ;
; 1.072  ; RX_TX:RX_TX_Inst|Receive_Data[7]                         ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.908      ;
; 1.086  ; RX_TX:RX_TX_Inst|Receive_Data[5]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 5.922      ;
; 1.120  ; Address_Counter:Address_Counter_Inst|counter_count[17]   ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.719      ;
; 1.227  ; Address_Counter:Address_Counter_Inst|counter_count[20]   ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 2.826      ;
; 1.241  ; RX_TX:RX_TX_Inst|Receive_Data[4]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.077      ;
; 1.251  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_count[17] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.087      ;
; 1.251  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_count[18] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.087      ;
; 1.251  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.087      ;
; 1.251  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.087      ;
; 1.251  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_count[21] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.087      ;
; 1.251  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_count[22] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.087      ;
; 1.251  ; RX_TX:RX_TX_Inst|Receive_Data[3]                         ; Address_Counter:Address_Counter_Inst|counter_count[23] ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.087      ;
; 1.338  ; Address_Counter:Address_Counter_Inst|frame_count[5]      ; Address_Counter:Address_Counter_Inst|counter_did_reset ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.043      ;
; 1.366  ; RX_TX:RX_TX_Inst|Receive_Data[2]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.202      ;
; 1.368  ; RX_TX:RX_TX_Inst|Receive_Data[1]                         ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 4.615      ; 6.204      ;
; 1.431  ; Address_Counter:Address_Counter_Inst|frame_count[6]      ; Address_Counter:Address_Counter_Inst|counter_did_reset ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.136      ;
; 1.562  ; Address_Counter:Address_Counter_Inst|counter_count[4]    ; Address_Counter:Address_Counter_Inst|counter_count[5]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 3.161      ;
; 1.570  ; Address_Counter:Address_Counter_Inst|counter_count[7]    ; Address_Counter:Address_Counter_Inst|counter_count[8]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 3.169      ;
; 1.571  ; Address_Counter:Address_Counter_Inst|counter_count[14]   ; Address_Counter:Address_Counter_Inst|counter_count[15] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 3.170      ;
; 1.571  ; Address_Counter:Address_Counter_Inst|counter_count[18]   ; Address_Counter:Address_Counter_Inst|counter_count[19] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 3.170      ;
; 1.571  ; Address_Counter:Address_Counter_Inst|counter_count[19]   ; Address_Counter:Address_Counter_Inst|counter_count[20] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 3.170      ;
; 1.580  ; Address_Counter:Address_Counter_Inst|counter_count[8]    ; Address_Counter:Address_Counter_Inst|counter_count[9]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 3.179      ;
; 1.580  ; Address_Counter:Address_Counter_Inst|counter_count[9]    ; Address_Counter:Address_Counter_Inst|counter_count[10] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 1.378      ; 3.179      ;
; 1.625  ; Address_Counter:Address_Counter_Inst|frame_count[4]      ; Address_Counter:Address_Counter_Inst|counter_did_reset ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.330      ;
; 1.645  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[12] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.350      ;
; 1.645  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[11] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.350      ;
; 1.645  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[13] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.350      ;
; 1.645  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[14] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.350      ;
; 1.645  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[15] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.350      ;
; 1.645  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[16] ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.350      ;
; 1.645  ; Address_Counter:Address_Counter_Inst|frame_count[7]      ; Address_Counter:Address_Counter_Inst|counter_count[7]  ; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.000        ; 3.484      ; 5.350      ;
+--------+----------------------------------------------------------+--------------------------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'Clk'                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------+---------------------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                     ; To Node                                                       ; Launch Clock                                    ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------+---------------------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; -1.532 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[10]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 2.413      ;
; -1.527 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[6]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 2.418      ;
; -1.524 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[11]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 2.421      ;
; -1.357 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[5]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 2.588      ;
; -1.032 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[10]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 2.413      ;
; -1.027 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[6]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 2.418      ;
; -1.024 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[11]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 2.421      ;
; -0.857 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[5]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 2.588      ;
; -0.853 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[1]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.092      ;
; -0.810 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[8]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.135      ;
; -0.809 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[9]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.136      ;
; -0.801 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[4]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.144      ;
; -0.798 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[3]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.147      ;
; -0.791 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[7]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.154      ;
; -0.790 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[2]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.155      ;
; -0.440 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_read          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.505      ;
; -0.376 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[13]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.569      ;
; -0.353 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[1]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.092      ;
; -0.310 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[8]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.135      ;
; -0.309 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[9]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.136      ;
; -0.301 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[4]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.144      ;
; -0.298 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[3]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.147      ;
; -0.291 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[7]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.154      ;
; -0.290 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[2]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.155      ;
; -0.185 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[0]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.760      ;
; -0.157 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|Ram_RAS                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.788      ;
; -0.098 ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|ram_nops[0]                      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 3.847      ;
; 0.060  ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_read          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.505      ;
; 0.124  ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[13]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.569      ;
; 0.315  ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[0]                  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.760      ;
; 0.339  ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[12]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; 0.000        ; 3.348      ; 4.284      ;
; 0.343  ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|Ram_RAS                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.788      ;
; 0.402  ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|ram_nops[0]                      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 3.847      ;
; 0.839  ; Ram_Control:Ram_Control_Inst|ram_state.activate               ; Ram_Control:Ram_Control_Inst|address_temp[12]                 ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk         ; -0.500       ; 3.348      ; 4.284      ;
; 1.377  ; RX_TX:RX_TX_Inst|CSn_f                                        ; RX_TX:RX_TX_Inst|CSn_ff                                       ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.598      ;
; 1.381  ; RX_TX:RX_TX_Inst|SCK_f                                        ; RX_TX:RX_TX_Inst|SCK_ff                                       ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.602      ;
; 1.384  ; RX_TX:RX_TX_Inst|MOSI_f                                       ; RX_TX:RX_TX_Inst|MOSI_ff                                      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.605      ;
; 1.391  ; RX_TX:RX_TX_Inst|MOSI_ff                                      ; RX_TX:RX_TX_Inst|Rx_Buf[0]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.612      ;
; 1.398  ; RX_TX:RX_TX_Inst|Rx_Buf[4]                                    ; RX_TX:RX_TX_Inst|Rx_Buf[5]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.619      ;
; 1.400  ; RX_TX:RX_TX_Inst|Rx_Buf[4]                                    ; RX_TX:RX_TX_Inst|Receive_Data[4]                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.621      ;
; 1.640  ; RX_TX:RX_TX_Inst|Rx_Buf[1]                                    ; RX_TX:RX_TX_Inst|Rx_Buf[2]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.861      ;
; 1.652  ; RX_TX:RX_TX_Inst|Rx_Buf[2]                                    ; RX_TX:RX_TX_Inst|Rx_Buf[3]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.873      ;
; 1.655  ; RX_TX:RX_TX_Inst|Rx_Buf[0]                                    ; RX_TX:RX_TX_Inst|Rx_Buf[1]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.876      ;
; 1.660  ; RX_TX:RX_TX_Inst|Rx_Buf[7]                                    ; RX_TX:RX_TX_Inst|Receive_Data[7]                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.881      ;
; 1.661  ; RX_TX:RX_TX_Inst|Rx_Buf[5]                                    ; RX_TX:RX_TX_Inst|Rx_Buf[6]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.882      ;
; 1.666  ; Ram_Control:Ram_Control_Inst|OEn                              ; Ram_Control:Ram_Control_Inst|OEn                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.887      ;
; 1.666  ; RX_TX:RX_TX_Inst|Rx_Buf[5]                                    ; RX_TX:RX_TX_Inst|Receive_Data[5]                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.887      ;
; 1.674  ; RX_TX:RX_TX_Inst|Rx_Buf[6]                                    ; RX_TX:RX_TX_Inst|Rx_Buf[7]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.895      ;
; 1.675  ; RX_TX:RX_TX_Inst|Rx_Buf[6]                                    ; RX_TX:RX_TX_Inst|Receive_Data[6]                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.896      ;
; 1.766  ; RX_TX:RX_TX_Inst|CSn_ff                                       ; RX_TX:RX_TX_Inst|CSIntOld                                     ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 1.987      ;
; 1.787  ; RX_TX:RX_TX_Inst|SCK_ff                                       ; RX_TX:RX_TX_Inst|SCKIntOld                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.008      ;
; 1.898  ; Ram_Control:Ram_Control_Inst|Ram_RAS                          ; Ram_Control:Ram_Control_Inst|Ram_RAS                          ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.119      ;
; 1.907  ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_read          ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_read          ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.128      ;
; 1.930  ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data           ; Ram_Control:Ram_Control_Inst|ram_state.toggle_OE              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.151      ;
; 1.945  ; Ram_Control:Ram_Control_Inst|ram_nops[9]                      ; Ram_Control:Ram_Control_Inst|ram_nops[9]                      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.166      ;
; 1.946  ; Ram_Control:Ram_Control_Inst|ram_nops[10]                     ; Ram_Control:Ram_Control_Inst|ram_nops[10]                     ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.167      ;
; 2.118  ; Ram_Control:Ram_Control_Inst|address_temp[1]                  ; Ram_Control:Ram_Control_Inst|address_temp[1]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.339      ;
; 2.127  ; Ram_Control:Ram_Control_Inst|ram_next_state.init              ; Ram_Control:Ram_Control_Inst|ram_next_state.init              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.348      ;
; 2.130  ; Ram_Control:Ram_Control_Inst|ram_next_state.init              ; Ram_Control:Ram_Control_Inst|ram_state.init                   ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.351      ;
; 2.133  ; Ram_Control:Ram_Control_Inst|ram_nops[5]                      ; Ram_Control:Ram_Control_Inst|ram_nops[5]                      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.354      ;
; 2.144  ; Ram_Control:Ram_Control_Inst|another_refresh                  ; Ram_Control:Ram_Control_Inst|ram_next_state.activate          ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.365      ;
; 2.149  ; Ram_Control:Ram_Control_Inst|ram_state.precharge              ; Ram_Control:Ram_Control_Inst|Ram_WE                           ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.370      ;
; 2.152  ; Ram_Control:Ram_Control_Inst|another_refresh                  ; Ram_Control:Ram_Control_Inst|ram_next_state.auto_refresh      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.373      ;
; 2.222  ; Ram_Control:Ram_Control_Inst|ram_next_state.set_mode_register ; Ram_Control:Ram_Control_Inst|ram_next_state.set_mode_register ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.443      ;
; 2.226  ; Ram_Control:Ram_Control_Inst|ram_state.init                   ; Ram_Control:Ram_Control_Inst|ram_nops[4]                      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.447      ;
; 2.231  ; Ram_Control:Ram_Control_Inst|address_temp[12]                 ; Ram_Control:Ram_Control_Inst|address_temp[12]                 ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.452      ;
; 2.231  ; Ram_Control:Ram_Control_Inst|address_temp[13]                 ; Ram_Control:Ram_Control_Inst|address_temp[13]                 ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.452      ;
; 2.239  ; Ram_Control:Ram_Control_Inst|ram_next_state.auto_refresh      ; Ram_Control:Ram_Control_Inst|ram_next_state.auto_refresh      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.460      ;
; 2.272  ; Ram_Control:Ram_Control_Inst|ram_state.toggle_OE              ; Ram_Control:Ram_Control_Inst|ram_state.ram_write              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.493      ;
; 2.322  ; RX_TX:RX_TX_Inst|Rx_Buf[0]                                    ; RX_TX:RX_TX_Inst|Receive_Data[0]                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.543      ;
; 2.326  ; Ram_Control:Ram_Control_Inst|ram_state.init                   ; Ram_Control:Ram_Control_Inst|ram_nops[6]                      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.547      ;
; 2.334  ; Ram_Control:Ram_Control_Inst|address_buf[22]                  ; Ram_Control:Ram_Control_Inst|address_temp[12]                 ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.555      ;
; 2.368  ; RX_TX:RX_TX_Inst|Rx_Buf[1]                                    ; RX_TX:RX_TX_Inst|Receive_Data[1]                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.589      ;
; 2.376  ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_get_data      ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data           ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.597      ;
; 2.408  ; RX_TX:RX_TX_Inst|Rx_Buf[2]                                    ; RX_TX:RX_TX_Inst|Receive_Data[2]                              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.629      ;
; 2.492  ; RX_TX:RX_TX_Inst|Rx_Buf[3]                                    ; RX_TX:RX_TX_Inst|Rx_Buf[4]                                    ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.713      ;
; 2.505  ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_read          ; Ram_Control:Ram_Control_Inst|ram_state.ram_read               ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.726      ;
; 2.513  ; Ram_Control:Ram_Control_Inst|Ram_WE                           ; Ram_Control:Ram_Control_Inst|Ram_WE                           ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.734      ;
; 2.523  ; Ram_Control:Ram_Control_Inst|ram_next_state.precharge         ; Ram_Control:Ram_Control_Inst|ram_state.precharge              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.744      ;
; 2.557  ; Ram_Control:Ram_Control_Inst|address_buf[11]                  ; Ram_Control:Ram_Control_Inst|address_temp[11]                 ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.778      ;
; 2.559  ; Ram_Control:Ram_Control_Inst|address_buf[2]                   ; Ram_Control:Ram_Control_Inst|address_temp[2]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.780      ;
; 2.574  ; Ram_Control:Ram_Control_Inst|ram_next_state.set_mode_register ; Ram_Control:Ram_Control_Inst|ram_state.set_mode_register      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.795      ;
; 2.579  ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_get_data      ; Ram_Control:Ram_Control_Inst|ram_next_state.ram_get_data      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.800      ;
; 2.607  ; Ram_Control:Ram_Control_Inst|address_buf[4]                   ; Ram_Control:Ram_Control_Inst|address_temp[4]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.828      ;
; 2.634  ; Ram_Control:Ram_Control_Inst|ram_nops[3]                      ; Ram_Control:Ram_Control_Inst|ram_nops[3]                      ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.855      ;
; 2.652  ; Ram_Control:Ram_Control_Inst|ram_next_state.activate          ; Ram_Control:Ram_Control_Inst|ram_next_state.activate          ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.873      ;
; 2.683  ; Ram_Control:Ram_Control_Inst|ram_state.nop                    ; Ram_Control:Ram_Control_Inst|ram_state.ram_get_data           ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.904      ;
; 2.697  ; Ram_Control:Ram_Control_Inst|address_buf[16]                  ; Ram_Control:Ram_Control_Inst|address_temp[6]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.918      ;
; 2.698  ; Ram_Control:Ram_Control_Inst|ram_state.auto_refresh           ; Ram_Control:Ram_Control_Inst|Ram_RAS                          ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.919      ;
; 2.704  ; Ram_Control:Ram_Control_Inst|Ram_DQM                          ; Ram_Control:Ram_Control_Inst|Ram_DQM                          ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.925      ;
; 2.713  ; Ram_Control:Ram_Control_Inst|address_buf[21]                  ; Ram_Control:Ram_Control_Inst|address_temp[11]                 ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 2.934      ;
; 2.800  ; Ram_Control:Ram_Control_Inst|ram_state.nop                    ; Ram_Control:Ram_Control_Inst|ram_state.precharge              ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.021      ;
; 2.806  ; Ram_Control:Ram_Control_Inst|ram_state.ram_read               ; Ram_Control:Ram_Control_Inst|ram_state.nop_dqm_down           ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.027      ;
; 2.851  ; Ram_Control:Ram_Control_Inst|ram_state.ram_write              ; Ram_Control:Ram_Control_Inst|Ram_CAS                          ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.072      ;
; 2.948  ; Ram_Control:Ram_Control_Inst|address_buf[0]                   ; Ram_Control:Ram_Control_Inst|address_temp[0]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.169      ;
; 2.948  ; Ram_Control:Ram_Control_Inst|address_buf[18]                  ; Ram_Control:Ram_Control_Inst|address_temp[8]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.169      ;
; 2.975  ; Ram_Control:Ram_Control_Inst|address_buf[23]                  ; Ram_Control:Ram_Control_Inst|address_temp[13]                 ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.196      ;
; 2.983  ; Ram_Control:Ram_Control_Inst|address_buf[5]                   ; Ram_Control:Ram_Control_Inst|address_temp[5]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.204      ;
; 3.000  ; Ram_Control:Ram_Control_Inst|address_buf[10]                  ; Ram_Control:Ram_Control_Inst|address_temp[10]                 ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.221      ;
; 3.024  ; Ram_Control:Ram_Control_Inst|address_buf[6]                   ; Ram_Control:Ram_Control_Inst|address_temp[6]                  ; Clk                                             ; Clk         ; 0.000        ; 0.000      ; 3.245      ;
+--------+---------------------------------------------------------------+---------------------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'V_Sync'                                                                                                                                                                          ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.668 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[0] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 1.889      ;
; 2.126 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[1] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.347      ;
; 2.127 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[2] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.348      ;
; 2.230 ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.451      ;
; 2.231 ; Address_Counter:Address_Counter_Inst|frame_count[6] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.452      ;
; 2.231 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.452      ;
; 2.231 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.452      ;
; 2.247 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[1] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.468      ;
; 2.633 ; Address_Counter:Address_Counter_Inst|frame_count[7] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 2.854      ;
; 2.958 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[2] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.179      ;
; 2.959 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.180      ;
; 3.069 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.290      ;
; 3.070 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.291      ;
; 3.170 ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.391      ;
; 3.171 ; Address_Counter:Address_Counter_Inst|frame_count[6] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.392      ;
; 3.171 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.392      ;
; 3.180 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.401      ;
; 3.187 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[2] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.408      ;
; 3.281 ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.502      ;
; 3.298 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[3] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.519      ;
; 3.409 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[4] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.630      ;
; 3.492 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.713      ;
; 3.492 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.713      ;
; 3.492 ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.713      ;
; 3.539 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.760      ;
; 3.539 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.760      ;
; 3.539 ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.760      ;
; 3.640 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.861      ;
; 3.640 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.861      ;
; 3.640 ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.861      ;
; 3.649 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.870      ;
; 3.649 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.870      ;
; 3.649 ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 3.870      ;
; 3.878 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[7] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 4.099      ;
; 3.878 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[6] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 4.099      ;
; 3.878 ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Address_Counter:Address_Counter_Inst|frame_count[5] ; V_Sync       ; V_Sync      ; 0.000        ; 0.000      ; 4.099      ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery: 'V_Sync'                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                             ; Launch Clock                                    ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[7] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[6] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
; -6.925 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 1.000        ; -3.484     ; 4.108      ;
+--------+--------------------------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal: 'V_Sync'                                                                                                                                                                                                             ;
+-------+--------------------------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                              ; To Node                                             ; Launch Clock                                    ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[7] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[6] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[5] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[4] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[3] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[2] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[1] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
; 5.993 ; Address_Counter:Address_Counter_Inst|counter_did_reset ; Address_Counter:Address_Counter_Inst|frame_count[0] ; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync      ; 0.000        ; -2.106     ; 4.108      ;
+-------+--------------------------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Minimum Pulse Width: 'Clk'                                                                                                    ;
+--------+--------------+----------------+------------------+-------+------------+----------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                       ;
+--------+--------------+----------------+------------------+-------+------------+----------------------------------------------+
; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; Clk   ; Rise       ; Clk                                          ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|CSIntOld                    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|CSIntOld                    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|CSn_f                       ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|CSn_f                       ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|CSn_ff                      ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|CSn_ff                      ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|MOSI_f                      ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|MOSI_f                      ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|MOSI_ff                     ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|MOSI_ff                     ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[0]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[0]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[1]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[1]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[2]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[2]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[3]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[3]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[4]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[4]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[5]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[5]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[6]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[6]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[7]             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Receive_Data[7]             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[0]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[0]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[1]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[1]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[2]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[2]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[3]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[3]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[4]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[4]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[5]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[5]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[6]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[6]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[7]                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|Rx_Buf[7]                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|SCKIntOld                   ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|SCKIntOld                   ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|SCK_f                       ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|SCK_f                       ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|SCK_ff                      ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; RX_TX:RX_TX_Inst|SCK_ff                      ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|OEn             ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|OEn             ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_CAS         ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_CAS         ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_DQM         ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_DQM         ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_RAS         ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_RAS         ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_WE          ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|Ram_WE          ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[0]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[0]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[1]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[1]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[2]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[2]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[3]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[3]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[4]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[4]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[5]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[5]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[6]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[6]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[7]    ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Fall       ; Ram_Control:Ram_Control_Inst|Read_Data[7]    ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[0]  ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[0]  ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[10] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[10] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[11] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[11] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[12] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[12] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[13] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[13] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[14] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[14] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[15] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[15] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[16] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[16] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[17] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[17] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[18] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[18] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[19] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[19] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[1]  ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[1]  ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; Clk   ; Rise       ; Ram_Control:Ram_Control_Inst|address_buf[20] ;
+--------+--------------+----------------+------------------+-------+------------+----------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Pulse Width: 'V_Sync'                                                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+--------+------------+-----------------------------------------------------+
; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; V_Sync ; Rise       ; V_Sync                                              ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[0] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[0] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[1] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[1] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[2] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[2] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[3] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[3] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[4] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[4] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[5] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[5] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[6] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[6] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[7] ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter:Address_Counter_Inst|frame_count[7] ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; bypass                                              ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; bypass                                              ;
; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; V_Sync ; Rise       ; we                                                  ;
; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; V_Sync ; Rise       ; we                                                  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[0]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[0]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[1]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[1]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[2]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[2]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[3]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[3]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[4]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[4]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[5]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[5]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[6]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[6]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[7]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; Address_Counter_Inst|frame_count[7]|clk             ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; V_Sync|combout                                      ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; V_Sync|combout                                      ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; bypass|clk                                          ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; bypass|clk                                          ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; V_Sync ; Rise       ; we|clk                                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; V_Sync ; Rise       ; we|clk                                              ;
+--------+--------------+----------------+------------------+--------+------------+-----------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Pulse Width: 'Ram_Control:Ram_Control_Inst|ram_state.activate'                                                                                                            ;
+--------+--------------+----------------+------------------+-------------------------------------------------+------------+--------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                           ; Clock Edge ; Target                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------+------------+--------------------------------------------------------+
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[0]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[0]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[10] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[10] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[11] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[11] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[12] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[12] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[13] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[13] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[14] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[14] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[15] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[15] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[16] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[16] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[17] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[17] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[18] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[18] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[19] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[19] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[1]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[1]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[20] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[20] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[21] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[21] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[22] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[22] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[23] ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[23] ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[2]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[2]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[3]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[3]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[4]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[4]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[5]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[5]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[6]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[6]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[7]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[7]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[8]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[8]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[9]  ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_count[9]  ;
; -1.144 ; -0.878       ; 0.266          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_did_reset ;
; -1.144 ; -0.878       ; 0.266          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter:Address_Counter_Inst|counter_did_reset ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[0]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[0]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[10]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[10]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[11]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[11]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[12]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[12]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[13]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[13]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[14]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[14]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[15]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[15]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[16]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[16]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[17]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[17]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[18]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[18]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[19]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[19]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[1]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[1]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[20]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[20]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[21]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[21]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[22]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[22]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[23]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[23]|clk             ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[2]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[2]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[3]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[3]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[4]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[4]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[5]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[5]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[6]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[6]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[7]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[7]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[8]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[8]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[9]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_count[9]|clk              ;
; -0.878 ; -0.878       ; 0.000          ; High Pulse Width ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_did_reset|clk             ;
; -0.878 ; -0.878       ; 0.000          ; Low Pulse Width  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; Rise       ; Address_Counter_Inst|counter_did_reset|clk             ;
+--------+--------------+----------------+------------------+-------------------------------------------------+------------+--------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+--------------+-------------------------------------------------+-------+-------+------------+-------------------------------------------------+
; Data Port    ; Clock Port                                      ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                 ;
+--------------+-------------------------------------------------+-------+-------+------------+-------------------------------------------------+
; CSn          ; Clk                                             ; 3.087 ; 3.087 ; Rise       ; Clk                                             ;
; MOSI         ; Clk                                             ; 1.839 ; 1.839 ; Rise       ; Clk                                             ;
; ResetN       ; Clk                                             ; 5.540 ; 5.540 ; Rise       ; Clk                                             ;
; SCK          ; Clk                                             ; 3.035 ; 3.035 ; Rise       ; Clk                                             ;
; Ram_Data[*]  ; Clk                                             ; 4.903 ; 4.903 ; Fall       ; Clk                                             ;
;  Ram_Data[0] ; Clk                                             ; 3.293 ; 3.293 ; Fall       ; Clk                                             ;
;  Ram_Data[1] ; Clk                                             ; 4.903 ; 4.903 ; Fall       ; Clk                                             ;
;  Ram_Data[2] ; Clk                                             ; 3.420 ; 3.420 ; Fall       ; Clk                                             ;
;  Ram_Data[3] ; Clk                                             ; 3.828 ; 3.828 ; Fall       ; Clk                                             ;
;  Ram_Data[4] ; Clk                                             ; 2.705 ; 2.705 ; Fall       ; Clk                                             ;
;  Ram_Data[5] ; Clk                                             ; 3.242 ; 3.242 ; Fall       ; Clk                                             ;
;  Ram_Data[6] ; Clk                                             ; 3.251 ; 3.251 ; Fall       ; Clk                                             ;
;  Ram_Data[7] ; Clk                                             ; 2.714 ; 2.714 ; Fall       ; Clk                                             ;
; AD_Data[*]   ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.711 ; 1.711 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[0]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.219 ; 1.219 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[1]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.046 ; 0.046 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[2]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.290 ; 0.290 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[3]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.479 ; 0.479 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[4]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.711 ; 1.711 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[5]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.903 ; 0.903 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[6]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.926 ; 0.926 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[7]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 0.768 ; 0.768 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; Rec_Button   ; V_Sync                                          ; 3.059 ; 3.059 ; Rise       ; V_Sync                                          ;
; Rec_Switch   ; V_Sync                                          ; 2.537 ; 2.537 ; Rise       ; V_Sync                                          ;
+--------------+-------------------------------------------------+-------+-------+------------+-------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+--------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+
; Data Port    ; Clock Port                                      ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                 ;
+--------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+
; CSn          ; Clk                                             ; -2.533 ; -2.533 ; Rise       ; Clk                                             ;
; MOSI         ; Clk                                             ; -1.285 ; -1.285 ; Rise       ; Clk                                             ;
; ResetN       ; Clk                                             ; -0.501 ; -0.501 ; Rise       ; Clk                                             ;
; SCK          ; Clk                                             ; -2.481 ; -2.481 ; Rise       ; Clk                                             ;
; Ram_Data[*]  ; Clk                                             ; -2.151 ; -2.151 ; Fall       ; Clk                                             ;
;  Ram_Data[0] ; Clk                                             ; -2.739 ; -2.739 ; Fall       ; Clk                                             ;
;  Ram_Data[1] ; Clk                                             ; -4.349 ; -4.349 ; Fall       ; Clk                                             ;
;  Ram_Data[2] ; Clk                                             ; -2.866 ; -2.866 ; Fall       ; Clk                                             ;
;  Ram_Data[3] ; Clk                                             ; -3.274 ; -3.274 ; Fall       ; Clk                                             ;
;  Ram_Data[4] ; Clk                                             ; -2.151 ; -2.151 ; Fall       ; Clk                                             ;
;  Ram_Data[5] ; Clk                                             ; -2.688 ; -2.688 ; Fall       ; Clk                                             ;
;  Ram_Data[6] ; Clk                                             ; -2.697 ; -2.697 ; Fall       ; Clk                                             ;
;  Ram_Data[7] ; Clk                                             ; -2.160 ; -2.160 ; Fall       ; Clk                                             ;
; AD_Data[*]   ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 2.766  ; 2.766  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[0]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.471  ; 1.471  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[1]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 2.766  ; 2.766  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[2]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 2.013  ; 2.013  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[3]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 2.194  ; 2.194  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[4]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.110  ; 1.110  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[5]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.909  ; 1.909  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[6]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.348  ; 1.348  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  AD_Data[7]  ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 1.506  ; 1.506  ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; Rec_Button   ; V_Sync                                          ; -0.951 ; -0.951 ; Rise       ; V_Sync                                          ;
; Rec_Switch   ; V_Sync                                          ; -1.983 ; -1.983 ; Rise       ; V_Sync                                          ;
+--------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                               ;
+------------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+
; Data Port        ; Clock Port                                      ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                 ;
+------------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+
; Ram_Address[*]   ; Clk                                             ; 10.060 ; 10.060 ; Rise       ; Clk                                             ;
;  Ram_Address[0]  ; Clk                                             ; 8.143  ; 8.143  ; Rise       ; Clk                                             ;
;  Ram_Address[1]  ; Clk                                             ; 10.060 ; 10.060 ; Rise       ; Clk                                             ;
;  Ram_Address[2]  ; Clk                                             ; 8.856  ; 8.856  ; Rise       ; Clk                                             ;
;  Ram_Address[3]  ; Clk                                             ; 8.679  ; 8.679  ; Rise       ; Clk                                             ;
;  Ram_Address[4]  ; Clk                                             ; 8.635  ; 8.635  ; Rise       ; Clk                                             ;
;  Ram_Address[5]  ; Clk                                             ; 8.103  ; 8.103  ; Rise       ; Clk                                             ;
;  Ram_Address[6]  ; Clk                                             ; 8.649  ; 8.649  ; Rise       ; Clk                                             ;
;  Ram_Address[7]  ; Clk                                             ; 8.680  ; 8.680  ; Rise       ; Clk                                             ;
;  Ram_Address[8]  ; Clk                                             ; 8.658  ; 8.658  ; Rise       ; Clk                                             ;
;  Ram_Address[9]  ; Clk                                             ; 8.801  ; 8.801  ; Rise       ; Clk                                             ;
;  Ram_Address[10] ; Clk                                             ; 8.761  ; 8.761  ; Rise       ; Clk                                             ;
;  Ram_Address[11] ; Clk                                             ; 8.687  ; 8.687  ; Rise       ; Clk                                             ;
;  Ram_Address[12] ; Clk                                             ; 8.004  ; 8.004  ; Rise       ; Clk                                             ;
;  Ram_Address[13] ; Clk                                             ; 8.121  ; 8.121  ; Rise       ; Clk                                             ;
; Ram_CAS          ; Clk                                             ; 9.638  ; 9.638  ; Rise       ; Clk                                             ;
; Ram_Clk          ; Clk                                             ; 5.554  ; 5.554  ; Rise       ; Clk                                             ;
; Ram_DQM          ; Clk                                             ; 9.199  ; 9.199  ; Rise       ; Clk                                             ;
; Ram_RAS          ; Clk                                             ; 7.983  ; 7.983  ; Rise       ; Clk                                             ;
; Ram_WE           ; Clk                                             ; 8.311  ; 8.311  ; Rise       ; Clk                                             ;
; Ram_Clk          ; Clk                                             ; 5.554  ; 5.554  ; Fall       ; Clk                                             ;
; Led_Front        ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.907 ; 12.907 ; Rise       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; AD_Clk           ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.293 ; 12.293 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; DA_Clk           ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.852 ; 12.852 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; DA_Data[*]       ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.959 ; 14.959 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[0]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.804 ; 12.804 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[1]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.306 ; 13.306 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[2]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.811 ; 12.811 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[3]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.358 ; 13.358 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[4]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.651 ; 12.651 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[5]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.277 ; 13.277 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[6]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.959 ; 14.959 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[7]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.293 ; 13.293 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; Ram_Data[*]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.561 ; 14.561 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[0]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.561 ; 14.561 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[1]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.676 ; 13.676 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[2]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.045 ; 14.045 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[3]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.656 ; 13.656 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[4]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.016 ; 14.016 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[5]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.869 ; 12.869 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[6]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.413 ; 13.413 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[7]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.046 ; 14.046 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
+------------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                       ;
+------------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+
; Data Port        ; Clock Port                                      ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                 ;
+------------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+
; Ram_Address[*]   ; Clk                                             ; 8.004  ; 8.004  ; Rise       ; Clk                                             ;
;  Ram_Address[0]  ; Clk                                             ; 8.143  ; 8.143  ; Rise       ; Clk                                             ;
;  Ram_Address[1]  ; Clk                                             ; 10.060 ; 10.060 ; Rise       ; Clk                                             ;
;  Ram_Address[2]  ; Clk                                             ; 8.856  ; 8.856  ; Rise       ; Clk                                             ;
;  Ram_Address[3]  ; Clk                                             ; 8.679  ; 8.679  ; Rise       ; Clk                                             ;
;  Ram_Address[4]  ; Clk                                             ; 8.635  ; 8.635  ; Rise       ; Clk                                             ;
;  Ram_Address[5]  ; Clk                                             ; 8.103  ; 8.103  ; Rise       ; Clk                                             ;
;  Ram_Address[6]  ; Clk                                             ; 8.649  ; 8.649  ; Rise       ; Clk                                             ;
;  Ram_Address[7]  ; Clk                                             ; 8.680  ; 8.680  ; Rise       ; Clk                                             ;
;  Ram_Address[8]  ; Clk                                             ; 8.658  ; 8.658  ; Rise       ; Clk                                             ;
;  Ram_Address[9]  ; Clk                                             ; 8.801  ; 8.801  ; Rise       ; Clk                                             ;
;  Ram_Address[10] ; Clk                                             ; 8.761  ; 8.761  ; Rise       ; Clk                                             ;
;  Ram_Address[11] ; Clk                                             ; 8.687  ; 8.687  ; Rise       ; Clk                                             ;
;  Ram_Address[12] ; Clk                                             ; 8.004  ; 8.004  ; Rise       ; Clk                                             ;
;  Ram_Address[13] ; Clk                                             ; 8.121  ; 8.121  ; Rise       ; Clk                                             ;
; Ram_CAS          ; Clk                                             ; 9.638  ; 9.638  ; Rise       ; Clk                                             ;
; Ram_Clk          ; Clk                                             ; 5.554  ; 5.554  ; Rise       ; Clk                                             ;
; Ram_DQM          ; Clk                                             ; 9.199  ; 9.199  ; Rise       ; Clk                                             ;
; Ram_RAS          ; Clk                                             ; 7.983  ; 7.983  ; Rise       ; Clk                                             ;
; Ram_WE           ; Clk                                             ; 8.311  ; 8.311  ; Rise       ; Clk                                             ;
; Ram_Clk          ; Clk                                             ; 5.554  ; 5.554  ; Fall       ; Clk                                             ;
; Led_Front        ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 11.529 ; 11.529 ; Rise       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; AD_Clk           ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.056 ; 12.056 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; DA_Clk           ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.615 ; 12.615 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; DA_Data[*]       ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 11.806 ; 11.806 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[0]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 11.959 ; 11.959 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[1]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.461 ; 12.461 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[2]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 11.966 ; 11.966 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[3]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.513 ; 12.513 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[4]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 11.806 ; 11.806 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[5]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.432 ; 12.432 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[6]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 14.114 ; 14.114 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  DA_Data[7]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.448 ; 12.448 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
; Ram_Data[*]      ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.024 ; 12.024 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[0]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.716 ; 13.716 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[1]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.831 ; 12.831 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[2]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.200 ; 13.200 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[3]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.811 ; 12.811 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[4]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.171 ; 13.171 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[5]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.024 ; 12.024 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[6]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 12.568 ; 12.568 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
;  Ram_Data[7]     ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 13.201 ; 13.201 ; Fall       ; Ram_Control:Ram_Control_Inst|ram_state.activate ;
+------------------+-------------------------------------------------+--------+--------+------------+-------------------------------------------------+


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Rec_Button ; Led3        ; 8.808 ;    ;    ; 8.808 ;
; Rec_Switch ; Led1        ; 8.762 ;    ;    ; 8.762 ;
+------------+-------------+-------+----+----+-------+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Rec_Button ; Led3        ; 8.808 ;    ;    ; 8.808 ;
; Rec_Switch ; Led1        ; 8.762 ;    ;    ; 8.762 ;
+------------+-------------+-------+----+----+-------+


+-------------------------------------------------------------------------+
; Output Enable Times                                                     ;
+--------------+------------+-------+------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+------+------------+-----------------+
; Ram_Data[*]  ; Clk        ; 6.960 ;      ; Rise       ; Clk             ;
;  Ram_Data[0] ; Clk        ; 6.978 ;      ; Rise       ; Clk             ;
;  Ram_Data[1] ; Clk        ; 6.978 ;      ; Rise       ; Clk             ;
;  Ram_Data[2] ; Clk        ; 6.960 ;      ; Rise       ; Clk             ;
;  Ram_Data[3] ; Clk        ; 6.960 ;      ; Rise       ; Clk             ;
;  Ram_Data[4] ; Clk        ; 8.109 ;      ; Rise       ; Clk             ;
;  Ram_Data[5] ; Clk        ; 8.109 ;      ; Rise       ; Clk             ;
;  Ram_Data[6] ; Clk        ; 8.126 ;      ; Rise       ; Clk             ;
;  Ram_Data[7] ; Clk        ; 8.126 ;      ; Rise       ; Clk             ;
+--------------+------------+-------+------+------------+-----------------+


+-------------------------------------------------------------------------+
; Minimum Output Enable Times                                             ;
+--------------+------------+-------+------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+------+------------+-----------------+
; Ram_Data[*]  ; Clk        ; 6.960 ;      ; Rise       ; Clk             ;
;  Ram_Data[0] ; Clk        ; 6.978 ;      ; Rise       ; Clk             ;
;  Ram_Data[1] ; Clk        ; 6.978 ;      ; Rise       ; Clk             ;
;  Ram_Data[2] ; Clk        ; 6.960 ;      ; Rise       ; Clk             ;
;  Ram_Data[3] ; Clk        ; 6.960 ;      ; Rise       ; Clk             ;
;  Ram_Data[4] ; Clk        ; 8.109 ;      ; Rise       ; Clk             ;
;  Ram_Data[5] ; Clk        ; 8.109 ;      ; Rise       ; Clk             ;
;  Ram_Data[6] ; Clk        ; 8.126 ;      ; Rise       ; Clk             ;
;  Ram_Data[7] ; Clk        ; 8.126 ;      ; Rise       ; Clk             ;
+--------------+------------+-------+------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Output Disable Times                                                             ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Ram_Data[*]  ; Clk        ; 6.960     ;           ; Rise       ; Clk             ;
;  Ram_Data[0] ; Clk        ; 6.978     ;           ; Rise       ; Clk             ;
;  Ram_Data[1] ; Clk        ; 6.978     ;           ; Rise       ; Clk             ;
;  Ram_Data[2] ; Clk        ; 6.960     ;           ; Rise       ; Clk             ;
;  Ram_Data[3] ; Clk        ; 6.960     ;           ; Rise       ; Clk             ;
;  Ram_Data[4] ; Clk        ; 8.109     ;           ; Rise       ; Clk             ;
;  Ram_Data[5] ; Clk        ; 8.109     ;           ; Rise       ; Clk             ;
;  Ram_Data[6] ; Clk        ; 8.126     ;           ; Rise       ; Clk             ;
;  Ram_Data[7] ; Clk        ; 8.126     ;           ; Rise       ; Clk             ;
+--------------+------------+-----------+-----------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                     ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Ram_Data[*]  ; Clk        ; 6.960     ;           ; Rise       ; Clk             ;
;  Ram_Data[0] ; Clk        ; 6.978     ;           ; Rise       ; Clk             ;
;  Ram_Data[1] ; Clk        ; 6.978     ;           ; Rise       ; Clk             ;
;  Ram_Data[2] ; Clk        ; 6.960     ;           ; Rise       ; Clk             ;
;  Ram_Data[3] ; Clk        ; 6.960     ;           ; Rise       ; Clk             ;
;  Ram_Data[4] ; Clk        ; 8.109     ;           ; Rise       ; Clk             ;
;  Ram_Data[5] ; Clk        ; 8.109     ;           ; Rise       ; Clk             ;
;  Ram_Data[6] ; Clk        ; 8.126     ;           ; Rise       ; Clk             ;
;  Ram_Data[7] ; Clk        ; 8.126     ;           ; Rise       ; Clk             ;
+--------------+------------+-----------+-----------+------------+-----------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                               ;
+-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
; From Clock                                      ; To Clock                                        ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
; Clk                                             ; Clk                                             ; 857      ; 0        ; 8        ; 0        ;
; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk                                             ; 53       ; 29       ; 0        ; 0        ;
; V_Sync                                          ; Clk                                             ; 2        ; 0        ; 0        ; 0        ;
; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 350      ; 0        ; 5        ; 8        ;
; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 516      ; 0        ; 0        ; 8        ;
; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 350      ; 0        ; 8        ; 0        ;
; V_Sync                                          ; V_Sync                                          ; 60       ; 0        ; 0        ; 0        ;
+-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                ;
+-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
; From Clock                                      ; To Clock                                        ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
; Clk                                             ; Clk                                             ; 857      ; 0        ; 8        ; 0        ;
; Ram_Control:Ram_Control_Inst|ram_state.activate ; Clk                                             ; 53       ; 29       ; 0        ; 0        ;
; V_Sync                                          ; Clk                                             ; 2        ; 0        ; 0        ; 0        ;
; Clk                                             ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 350      ; 0        ; 5        ; 8        ;
; Ram_Control:Ram_Control_Inst|ram_state.activate ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 516      ; 0        ; 0        ; 8        ;
; V_Sync                                          ; Ram_Control:Ram_Control_Inst|ram_state.activate ; 350      ; 0        ; 8        ; 0        ;
; V_Sync                                          ; V_Sync                                          ; 60       ; 0        ; 0        ; 0        ;
+-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+--------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                     ;
+-------------------------------------------------+----------+----------+----------+----------+----------+
; From Clock                                      ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------+----------+----------+----------+----------+----------+
; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync   ; 8        ; 0        ; 0        ; 0        ;
+-------------------------------------------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+--------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                      ;
+-------------------------------------------------+----------+----------+----------+----------+----------+
; From Clock                                      ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------+----------+----------+----------+----------+----------+
; Ram_Control:Ram_Control_Inst|ram_state.activate ; V_Sync   ; 8        ; 0        ; 0        ; 0        ;
+-------------------------------------------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 23    ; 23   ;
; Unconstrained Input Port Paths  ; 161   ; 161  ;
; Unconstrained Output Ports      ; 40    ; 40   ;
; Unconstrained Output Port Paths ; 48    ; 48   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Dec 29 22:02:12 2013
Info: Command: quartus_sta sk610-delay -c sk610-delay
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (306004): Started post-fitting delay annotation
Info (306005): Delay annotation completed successfully
Warning (335093): TimeQuest Timing Analyzer is analyzing 17 combinational loops as latches.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'sk610-delay.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name Ram_Control:Ram_Control_Inst|ram_state.activate Ram_Control:Ram_Control_Inst|ram_state.activate
    Info (332105): create_clock -period 1.000 -name Clk Clk
    Info (332105): create_clock -period 1.000 -name V_Sync V_Sync
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -7.396
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.396      -544.256 Clk 
    Info (332119):    -5.974      -158.291 Ram_Control:Ram_Control_Inst|ram_state.activate 
    Info (332119):    -3.470       -22.073 V_Sync 
Info (332146): Worst-case hold slack is -3.834
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.834       -31.201 Ram_Control:Ram_Control_Inst|ram_state.activate 
    Info (332119):    -1.532       -12.848 Clk 
    Info (332119):     1.668         0.000 V_Sync 
Info (332146): Worst-case recovery slack is -6.925
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -6.925       -55.400 V_Sync 
Info (332146): Worst-case removal slack is 5.993
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.993         0.000 V_Sync 
Info (332146): Worst-case minimum pulse width slack is -2.289
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.289        -2.289 Clk 
    Info (332119):    -2.289        -2.289 V_Sync 
    Info (332119):    -1.144      -125.626 Ram_Control:Ram_Control_Inst|ram_state.activate 
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 286 megabytes
    Info: Processing ended: Sun Dec 29 22:02:15 2013
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02


