-- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- VENDOR "Altera" -- PROGRAM "Quartus II 32-bit" -- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" -- DATE "12/29/2013 22:02:19" -- -- Device: Altera EPM240T100C5 Package TQFP100 -- -- -- This VHDL file should be used for ModelSim-Altera (VHDL) only -- LIBRARY IEEE; LIBRARY MAXII; USE IEEE.STD_LOGIC_1164.ALL; USE MAXII.MAXII_COMPONENTS.ALL; ENTITY Top IS PORT ( Clk : IN std_logic; ResetN : IN std_logic; Led1 : OUT std_logic; Led2 : OUT std_logic; Led3 : OUT std_logic; Led_Front : OUT std_logic; AD_Clk : OUT std_logic; AD_Data : IN std_logic_vector(7 DOWNTO 0); DA_Clk : OUT std_logic; DA_Data : OUT std_logic_vector(7 DOWNTO 0); Rec_Switch : IN std_logic; Rec_Button : IN std_logic; V_Sync : IN std_logic; Ram_Address : OUT std_logic_vector(13 DOWNTO 0); Ram_RAS : OUT std_logic; Ram_CAS : OUT std_logic; Ram_WE : OUT std_logic; Ram_Data : INOUT std_logic_vector(7 DOWNTO 0); Ram_Clk : OUT std_logic; Ram_DQM : OUT std_logic; MISO : OUT std_logic; MOSI : IN std_logic; SCK : IN std_logic; CSn : IN std_logic ); END Top; -- Design Ports Information -- Rec_Switch => Location: PIN_66, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- Rec_Button => Location: PIN_68, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- Clk => Location: PIN_12, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- ResetN => Location: PIN_14, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[0] => Location: PIN_35, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- V_Sync => Location: PIN_5, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[1] => Location: PIN_34, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[2] => Location: PIN_33, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[3] => Location: PIN_30, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[4] => Location: PIN_29, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[5] => Location: PIN_28, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[6] => Location: PIN_27, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- AD_Data[7] => Location: PIN_26, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- CSn => Location: PIN_72, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- SCK => Location: PIN_71, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- MOSI => Location: PIN_69, I/O Standard: 3.3-V LVTTL, Current Strength: Default -- Led1 => Location: PIN_19, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Led2 => Location: PIN_20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Led3 => Location: PIN_21, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Led_Front => Location: PIN_67, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- AD_Clk => Location: PIN_36, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Clk => Location: PIN_47, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[0] => Location: PIN_44, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[1] => Location: PIN_43, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[2] => Location: PIN_42, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[3] => Location: PIN_41, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[4] => Location: PIN_40, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[5] => Location: PIN_39, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[6] => Location: PIN_38, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- DA_Data[7] => Location: PIN_37, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[0] => Location: PIN_96, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[1] => Location: PIN_95, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[2] => Location: PIN_89, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[3] => Location: PIN_90, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[4] => Location: PIN_91, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[5] => Location: PIN_92, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[6] => Location: PIN_81, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[7] => Location: PIN_82, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[8] => Location: PIN_83, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[9] => Location: PIN_84, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[10] => Location: PIN_85, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[11] => Location: PIN_86, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[12] => Location: PIN_88, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Address[13] => Location: PIN_87, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_RAS => Location: PIN_97, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_CAS => Location: PIN_98, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_WE => Location: PIN_99, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Clk => Location: PIN_78, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_DQM => Location: PIN_77, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- MISO => Location: PIN_70, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[0] => Location: PIN_3, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[1] => Location: PIN_2, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[2] => Location: PIN_1, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[3] => Location: PIN_100, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[4] => Location: PIN_76, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[5] => Location: PIN_75, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[6] => Location: PIN_74, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -- Ram_Data[7] => Location: PIN_73, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA ARCHITECTURE structure OF Top IS SIGNAL gnd : std_logic := '0'; SIGNAL vcc : std_logic := '1'; SIGNAL unknown : std_logic := 'X'; SIGNAL devoe : std_logic := '1'; SIGNAL devclrn : std_logic := '1'; SIGNAL devpor : std_logic := '1'; SIGNAL ww_devoe : std_logic; SIGNAL ww_devclrn : std_logic; SIGNAL ww_devpor : std_logic; SIGNAL ww_Clk : std_logic; SIGNAL ww_ResetN : std_logic; SIGNAL ww_Led1 : std_logic; SIGNAL ww_Led2 : std_logic; SIGNAL ww_Led3 : std_logic; SIGNAL ww_Led_Front : std_logic; SIGNAL ww_AD_Clk : std_logic; SIGNAL ww_AD_Data : std_logic_vector(7 DOWNTO 0); SIGNAL ww_DA_Clk : std_logic; SIGNAL ww_DA_Data : std_logic_vector(7 DOWNTO 0); SIGNAL ww_Rec_Switch : std_logic; SIGNAL ww_Rec_Button : std_logic; SIGNAL ww_V_Sync : std_logic; SIGNAL ww_Ram_Address : std_logic_vector(13 DOWNTO 0); SIGNAL ww_Ram_RAS : std_logic; SIGNAL ww_Ram_CAS : std_logic; SIGNAL ww_Ram_WE : std_logic; SIGNAL ww_Ram_Clk : std_logic; SIGNAL ww_Ram_DQM : std_logic; SIGNAL ww_MISO : std_logic; SIGNAL ww_MOSI : std_logic; SIGNAL ww_SCK : std_logic; SIGNAL ww_CSn : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~5\ : std_logic; SIGNAL \RX_TX_Inst|CSIntOld~regout\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~10\ : std_logic; SIGNAL \RX_TX_Inst|SCKIntOld~regout\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~15\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~20\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~25\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~30\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~35\ : std_logic; SIGNAL \V_Sync~combout\ : std_logic; SIGNAL \Ram_Data[0]~0\ : std_logic; SIGNAL \Ram_Data[1]~1\ : std_logic; SIGNAL \Ram_Data[2]~2\ : std_logic; SIGNAL \Ram_Data[3]~3\ : std_logic; SIGNAL \Ram_Data[4]~4\ : std_logic; SIGNAL \Ram_Data[5]~5\ : std_logic; SIGNAL \Ram_Data[6]~6\ : std_logic; SIGNAL \Ram_Data[7]~7\ : std_logic; SIGNAL \Rec_Switch~combout\ : std_logic; SIGNAL \Rec_Button~combout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector7~1_combout\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr16~combout\ : std_logic; SIGNAL \ResetN~combout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_next_state.init~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.init~regout\ : std_logic; SIGNAL \Ram_Control_Inst|another_refresh~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_next_state.set_mode_register~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.set_mode_register~regout\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr2~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_next_state.precharge~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.precharge~regout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector24~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_next_state.auto_refresh~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.auto_refresh~regout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~65_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector30~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector21~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~67\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~67COUT1_82\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~60_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector20~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~62\ : std_logic; SIGNAL \Ram_Control_Inst|Selector19~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~55_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~57\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~57COUT1_84\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~50_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~52\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~52COUT1_86\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~45_combout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_nops[7]~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~47\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~47COUT1_88\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~40_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~42\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~42COUT1_90\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~35_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~37\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~30_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~32\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~32COUT1_92\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~25_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~27\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~27COUT1_94\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~20_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Equal0~1_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~22\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~22COUT1_96\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~15_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~17\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~17COUT1_98\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~10_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~12\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~5_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~7\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~7COUT1_100\ : std_logic; SIGNAL \Ram_Control_Inst|Add0~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Equal0~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Equal0~3_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Equal0~2_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Equal0~4_combout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_next_state.activate~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.activate~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_next_state.ram_read~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.ram_read~regout\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr10~0\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.nop~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.nop_dqm_down~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_next_state.ram_get_data~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.ram_get_data~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.toggle_OE~regout\ : std_logic; SIGNAL \Ram_Control_Inst|ram_state.ram_write~regout\ : std_logic; SIGNAL \AD_DA_Inst|Mux10~0\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr30~0\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr30~1_combout\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr31~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr29~0_combout\ : std_logic; SIGNAL \rtl~0_combout\ : std_logic; SIGNAL \MOSI~combout\ : std_logic; SIGNAL \RX_TX_Inst|MOSI_f~regout\ : std_logic; SIGNAL \RX_TX_Inst|MOSI_ff~regout\ : std_logic; SIGNAL \SCK~combout\ : std_logic; SIGNAL \RX_TX_Inst|SCK_f~regout\ : std_logic; SIGNAL \RX_TX_Inst|SCK_ff~regout\ : std_logic; SIGNAL \CSn~combout\ : std_logic; SIGNAL \RX_TX_Inst|CSn_f~regout\ : std_logic; SIGNAL \RX_TX_Inst|CSn_ff~regout\ : std_logic; SIGNAL \RX_TX_Inst|Rx_Buf[7]~0\ : std_logic; SIGNAL \RX_TX_Inst|Receive_Data[7]~0\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[7]~2_combout\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[1]~14\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[1]~14COUT1_23\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[2]~12\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[2]~12COUT1_25\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[3]~10\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[3]~10COUT1_27\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[4]~8\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[5]~6\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[5]~6COUT1_29\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[6]~4\ : std_logic; SIGNAL \Address_Counter_Inst|frame_count[6]~4COUT1_31\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~37_cout0\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~37COUT1_48\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~32_cout0\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~32COUT1_50\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~27_cout0\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~27COUT1_52\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~22_cout0\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~22COUT1_54\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~17_cout\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~12_cout0\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~12COUT1_56\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~7_cout0\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~7COUT1_58\ : std_logic; SIGNAL \Address_Counter_Inst|LessThan0~0_combout\ : std_logic; SIGNAL \Address_Counter_Inst|counter_did_reset~regout\ : std_logic; SIGNAL \AD_DA_Inst|Mux1~0_combout\ : std_logic; SIGNAL \AD_DA_Inst|AD_Clk~combout\ : std_logic; SIGNAL \AD_DA_Inst|Mux10~1_combout\ : std_logic; SIGNAL \bypass~regout\ : std_logic; SIGNAL \Ram_Control_Inst|load_enable~regout\ : std_logic; SIGNAL \AD_DA_Inst|Mux2~0\ : std_logic; SIGNAL \AD_DA_Inst|Mux3~0\ : std_logic; SIGNAL \AD_DA_Inst|Mux4~0\ : std_logic; SIGNAL \AD_DA_Inst|Mux5~0\ : std_logic; SIGNAL \AD_DA_Inst|Mux6~0\ : std_logic; SIGNAL \AD_DA_Inst|Mux7~0\ : std_logic; SIGNAL \AD_DA_Inst|Mux8~0\ : std_logic; SIGNAL \AD_DA_Inst|Mux9~0\ : std_logic; SIGNAL \Clk~combout\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr24~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|address_buf[0]~0_combout\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[0]~1\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[0]~1COUT1_68\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[1]~3\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[2]~7\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[2]~7COUT1_70\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[3]~11\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[3]~11COUT1_72\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[4]~15\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[4]~15COUT1_74\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[5]~19\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[5]~19COUT1_76\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[6]~23\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[7]~27\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[7]~27COUT1_78\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[8]~31\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[8]~31COUT1_80\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[9]~35\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[9]~35COUT1_82\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[10]~39\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[10]~39COUT1_84\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[11]~43\ : std_logic; SIGNAL \Ram_Control_Inst|WideOr24~1_combout\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[12]~5\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[12]~5COUT1_86\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[13]~9\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[13]~9COUT1_88\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[14]~13\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[14]~13COUT1_90\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[15]~17\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[15]~17COUT1_92\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[16]~21\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[17]~25\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[17]~25COUT1_94\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[18]~29\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[18]~29COUT1_96\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[19]~33\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[19]~33COUT1_98\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[20]~37\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[20]~37COUT1_100\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[21]~41\ : std_logic; SIGNAL \Ram_Control_Inst|Selector30~1\ : std_logic; SIGNAL \Ram_Control_Inst|Selector30~2_combout\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[22]~45\ : std_logic; SIGNAL \Address_Counter_Inst|counter_count[22]~45COUT1_102\ : std_logic; SIGNAL \Ram_Control_Inst|Ram_RAS~regout\ : std_logic; SIGNAL \we~regout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector1~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Ram_CAS~regout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector2~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Ram_WE~regout\ : std_logic; SIGNAL \Ram_Control_Inst|Selector3~0_combout\ : std_logic; SIGNAL \Ram_Control_Inst|Ram_DQM~regout\ : std_logic; SIGNAL \Ram_Control_Inst|OEn~regout\ : std_logic; SIGNAL \AD_Data~combout\ : std_logic_vector(7 DOWNTO 0); SIGNAL \Address_Counter_Inst|frame_count\ : std_logic_vector(7 DOWNTO 0); SIGNAL \Address_Counter_Inst|counter_count\ : std_logic_vector(23 DOWNTO 0); SIGNAL \AD_DA_Inst|ad_data\ : std_logic_vector(7 DOWNTO 0); SIGNAL \AD_DA_Inst|DA_Out\ : std_logic_vector(7 DOWNTO 0); SIGNAL \Ram_Control_Inst|Read_Data\ : std_logic_vector(7 DOWNTO 0); SIGNAL \Ram_Control_Inst|address_buf\ : std_logic_vector(23 DOWNTO 0); SIGNAL \Ram_Control_Inst|ram_nops\ : std_logic_vector(13 DOWNTO 0); SIGNAL \Ram_Control_Inst|address_temp\ : std_logic_vector(13 DOWNTO 0); SIGNAL \RX_TX_Inst|Rx_Buf\ : std_logic_vector(7 DOWNTO 0); SIGNAL \RX_TX_Inst|Receive_Data\ : std_logic_vector(7 DOWNTO 0); SIGNAL \ALT_INV_ResetN~combout\ : std_logic; SIGNAL \ALT_INV_Clk~combout\ : std_logic; SIGNAL \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\ : std_logic; BEGIN ww_Clk <= Clk; ww_ResetN <= ResetN; Led1 <= ww_Led1; Led2 <= ww_Led2; Led3 <= ww_Led3; Led_Front <= ww_Led_Front; AD_Clk <= ww_AD_Clk; ww_AD_Data <= AD_Data; DA_Clk <= ww_DA_Clk; DA_Data <= ww_DA_Data; ww_Rec_Switch <= Rec_Switch; ww_Rec_Button <= Rec_Button; ww_V_Sync <= V_Sync; Ram_Address <= ww_Ram_Address; Ram_RAS <= ww_Ram_RAS; Ram_CAS <= ww_Ram_CAS; Ram_WE <= ww_Ram_WE; Ram_Clk <= ww_Ram_Clk; Ram_DQM <= ww_Ram_DQM; MISO <= ww_MISO; ww_MOSI <= MOSI; ww_SCK <= SCK; ww_CSn <= CSn; ww_devoe <= devoe; ww_devclrn <= devclrn; ww_devpor <= devpor; \ALT_INV_ResetN~combout\ <= NOT \ResetN~combout\; \ALT_INV_Clk~combout\ <= NOT \Clk~combout\; \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\ <= NOT \Address_Counter_Inst|LessThan0~0_combout\; -- Location: PIN_5, I/O Standard: 3.3-V LVTTL, Current Strength: Default \V_Sync~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_V_Sync, combout => \V_Sync~combout\); -- Location: PIN_3, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[0]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(0), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(0), combout => \Ram_Data[0]~0\); -- Location: PIN_2, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[1]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(1), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(1), combout => \Ram_Data[1]~1\); -- Location: PIN_1, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[2]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(2), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(2), combout => \Ram_Data[2]~2\); -- Location: PIN_100, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[3]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(3), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(3), combout => \Ram_Data[3]~3\); -- Location: PIN_76, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[4]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(4), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(4), combout => \Ram_Data[4]~4\); -- Location: PIN_75, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[5]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(5), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(5), combout => \Ram_Data[5]~5\); -- Location: PIN_74, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[6]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(6), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(6), combout => \Ram_Data[6]~6\); -- Location: PIN_73, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Data[7]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "bidir") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|ad_data\(7), oe => \Ram_Control_Inst|OEn~regout\, padio => Ram_Data(7), combout => \Ram_Data[7]~7\); -- Location: PIN_66, I/O Standard: 3.3-V LVTTL, Current Strength: Default \Rec_Switch~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_Rec_Switch, combout => \Rec_Switch~combout\); -- Location: PIN_68, I/O Standard: 3.3-V LVTTL, Current Strength: Default \Rec_Button~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_Rec_Button, combout => \Rec_Button~combout\); -- Location: LC_X6_Y2_N3 \Ram_Control_Inst|Selector7~1\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector7~1_combout\ = (((\Ram_Control_Inst|ram_state.nop~regout\ & !\Ram_Control_Inst|Equal0~4_combout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "00f0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datac => \Ram_Control_Inst|ram_state.nop~regout\, datad => \Ram_Control_Inst|Equal0~4_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector7~1_combout\); -- Location: LC_X3_Y1_N3 \Ram_Control_Inst|WideOr16\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr16~combout\ = (\Ram_Control_Inst|ram_state.toggle_OE~regout\) # ((\Ram_Control_Inst|ram_state.ram_read~regout\) # ((\Ram_Control_Inst|ram_state.ram_get_data~regout\) # (\Ram_Control_Inst|ram_state.nop~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "fffe", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.toggle_OE~regout\, datab => \Ram_Control_Inst|ram_state.ram_read~regout\, datac => \Ram_Control_Inst|ram_state.ram_get_data~regout\, datad => \Ram_Control_Inst|ram_state.nop~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr16~combout\); -- Location: PIN_14, I/O Standard: 3.3-V LVTTL, Current Strength: Default \ResetN~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_ResetN, combout => \ResetN~combout\); -- Location: LC_X7_Y2_N9 \Ram_Control_Inst|ram_next_state.init\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_next_state.init~regout\ = DFFEAS(((\Ram_Control_Inst|ram_next_state.init~regout\) # ((GLOBAL(\ResetN~combout\) & !\Ram_Control_Inst|WideOr16~combout\))), GLOBAL(\Clk~combout\), VCC, , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ccfc", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_next_state.init~regout\, datac => \ResetN~combout\, datad => \Ram_Control_Inst|WideOr16~combout\, aclr => GND, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_next_state.init~regout\); -- Location: LC_X7_Y2_N3 \Ram_Control_Inst|ram_state.init\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.init~regout\ = DFFEAS(((\Ram_Control_Inst|ram_next_state.init~regout\) # ((!\Ram_Control_Inst|Equal0~4_combout\) # (!\Ram_Control_Inst|ram_state.nop~regout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "cfff", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_next_state.init~regout\, datac => \Ram_Control_Inst|ram_state.nop~regout\, datad => \Ram_Control_Inst|Equal0~4_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.init~regout\); -- Location: LC_X3_Y1_N5 \Ram_Control_Inst|another_refresh\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|another_refresh~regout\ = DFFEAS((((!\Ram_Control_Inst|ram_state.auto_refresh~regout\ & \Ram_Control_Inst|another_refresh~regout\)) # (!\Ram_Control_Inst|ram_state.init~regout\)), GLOBAL(\Clk~combout\), VCC, , GLOBAL(\ResetN~combout\), , -- , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "50ff", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datac => \Ram_Control_Inst|another_refresh~regout\, datad => \Ram_Control_Inst|ram_state.init~regout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|another_refresh~regout\); -- Location: LC_X4_Y1_N4 \Ram_Control_Inst|ram_next_state.set_mode_register\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_next_state.set_mode_register~regout\ = DFFEAS((\Ram_Control_Inst|ram_next_state.set_mode_register~regout\ & ((\Ram_Control_Inst|WideOr16~combout\) # ((!\Ram_Control_Inst|another_refresh~regout\ & -- \Ram_Control_Inst|ram_state.auto_refresh~regout\)))) # (!\Ram_Control_Inst|ram_next_state.set_mode_register~regout\ & (!\Ram_Control_Inst|another_refresh~regout\ & (\Ram_Control_Inst|ram_state.auto_refresh~regout\))), GLOBAL(\Clk~combout\), VCC, , -- GLOBAL(\ResetN~combout\), , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ba30", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_next_state.set_mode_register~regout\, datab => \Ram_Control_Inst|another_refresh~regout\, datac => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datad => \Ram_Control_Inst|WideOr16~combout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_next_state.set_mode_register~regout\); -- Location: LC_X2_Y1_N2 \Ram_Control_Inst|ram_state.set_mode_register\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.set_mode_register~regout\ = DFFEAS((\Ram_Control_Inst|ram_state.nop~regout\ & (((\Ram_Control_Inst|Equal0~4_combout\ & \Ram_Control_Inst|ram_next_state.set_mode_register~regout\)))), GLOBAL(\Clk~combout\), -- GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "a000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.nop~regout\, datac => \Ram_Control_Inst|Equal0~4_combout\, datad => \Ram_Control_Inst|ram_next_state.set_mode_register~regout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.set_mode_register~regout\); -- Location: LC_X3_Y1_N6 \Ram_Control_Inst|WideOr2~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr2~0_combout\ = ((\Ram_Control_Inst|ram_state.init~regout\ & (!\Ram_Control_Inst|ram_state.ram_write~regout\ & !\Ram_Control_Inst|ram_state.set_mode_register~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "000c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_state.init~regout\, datac => \Ram_Control_Inst|ram_state.ram_write~regout\, datad => \Ram_Control_Inst|ram_state.set_mode_register~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr2~0_combout\); -- Location: LC_X3_Y1_N4 \Ram_Control_Inst|ram_next_state.precharge\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_next_state.precharge~regout\ = DFFEAS((((\Ram_Control_Inst|WideOr16~combout\ & \Ram_Control_Inst|ram_next_state.precharge~regout\)) # (!\Ram_Control_Inst|WideOr2~0_combout\)), GLOBAL(\Clk~combout\), VCC, , GLOBAL(\ResetN~combout\), , -- , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "af0f", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|WideOr16~combout\, datac => \Ram_Control_Inst|WideOr2~0_combout\, datad => \Ram_Control_Inst|ram_next_state.precharge~regout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_next_state.precharge~regout\); -- Location: LC_X2_Y1_N0 \Ram_Control_Inst|ram_state.precharge\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.precharge~regout\ = DFFEAS(((\Ram_Control_Inst|ram_next_state.precharge~regout\ & (\Ram_Control_Inst|Equal0~4_combout\ & \Ram_Control_Inst|ram_state.nop~regout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "c000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_next_state.precharge~regout\, datac => \Ram_Control_Inst|Equal0~4_combout\, datad => \Ram_Control_Inst|ram_state.nop~regout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.precharge~regout\); -- Location: LC_X4_Y1_N0 \Ram_Control_Inst|Selector24~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector24~0_combout\ = ((\Ram_Control_Inst|ram_state.auto_refresh~regout\) # ((\Ram_Control_Inst|ram_state.precharge~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "fcfc", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datac => \Ram_Control_Inst|ram_state.precharge~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector24~0_combout\); -- Location: LC_X4_Y1_N3 \Ram_Control_Inst|ram_next_state.auto_refresh\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_next_state.auto_refresh~regout\ = DFFEAS((\Ram_Control_Inst|ram_next_state.auto_refresh~regout\ & ((\Ram_Control_Inst|WideOr16~combout\) # ((\Ram_Control_Inst|Selector24~0_combout\ & \Ram_Control_Inst|another_refresh~regout\)))) # -- (!\Ram_Control_Inst|ram_next_state.auto_refresh~regout\ & (((\Ram_Control_Inst|Selector24~0_combout\ & \Ram_Control_Inst|another_refresh~regout\)))), GLOBAL(\Clk~combout\), VCC, , GLOBAL(\ResetN~combout\), , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f888", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_next_state.auto_refresh~regout\, datab => \Ram_Control_Inst|WideOr16~combout\, datac => \Ram_Control_Inst|Selector24~0_combout\, datad => \Ram_Control_Inst|another_refresh~regout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_next_state.auto_refresh~regout\); -- Location: LC_X2_Y3_N0 \Ram_Control_Inst|ram_state.auto_refresh\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.auto_refresh~regout\ = DFFEAS((\Ram_Control_Inst|ram_next_state.auto_refresh~regout\ & (\Ram_Control_Inst|ram_state.nop~regout\ & ((\Ram_Control_Inst|Equal0~4_combout\)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , -- , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "8800", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_next_state.auto_refresh~regout\, datab => \Ram_Control_Inst|ram_state.nop~regout\, datad => \Ram_Control_Inst|Equal0~4_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.auto_refresh~regout\); -- Location: LC_X4_Y2_N3 \Ram_Control_Inst|Add0~65\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~65_combout\ = (!\Ram_Control_Inst|ram_nops\(0)) -- \Ram_Control_Inst|Add0~67\ = CARRY((\Ram_Control_Inst|ram_nops\(0))) -- \Ram_Control_Inst|Add0~67COUT1_82\ = CARRY((\Ram_Control_Inst|ram_nops\(0))) -- pragma translate_off GENERIC MAP ( lut_mask => "55aa", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(0), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~65_combout\, cout0 => \Ram_Control_Inst|Add0~67\, cout1 => \Ram_Control_Inst|Add0~67COUT1_82\); -- Location: LC_X3_Y2_N8 \Ram_Control_Inst|Selector30~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector30~0_combout\ = (((!\Ram_Control_Inst|ram_state.precharge~regout\ & !\Ram_Control_Inst|ram_state.activate~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "000f", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datac => \Ram_Control_Inst|ram_state.precharge~regout\, datad => \Ram_Control_Inst|ram_state.activate~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector30~0_combout\); -- Location: LC_X3_Y2_N2 \Ram_Control_Inst|Selector21~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector21~0_combout\ = (\Ram_Control_Inst|ram_state.auto_refresh~regout\) # (((\Ram_Control_Inst|ram_nops\(0) & !\Ram_Control_Inst|WideOr10~0\)) # (!\Ram_Control_Inst|Selector30~0_combout\)) -- pragma translate_off GENERIC MAP ( lut_mask => "aeff", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datab => \Ram_Control_Inst|ram_nops\(0), datac => \Ram_Control_Inst|WideOr10~0\, datad => \Ram_Control_Inst|Selector30~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector21~0_combout\); -- Location: LC_X3_Y2_N5 \Ram_Control_Inst|ram_nops[0]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(0) = DFFEAS((\Ram_Control_Inst|Selector21~0_combout\) # ((\Ram_Control_Inst|Add0~65_combout\ & (!\Ram_Control_Inst|Equal0~4_combout\ & \Ram_Control_Inst|ram_state.nop~regout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), -- , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff20", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|Add0~65_combout\, datab => \Ram_Control_Inst|Equal0~4_combout\, datac => \Ram_Control_Inst|ram_state.nop~regout\, datad => \Ram_Control_Inst|Selector21~0_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(0)); -- Location: LC_X4_Y2_N4 \Ram_Control_Inst|Add0~60\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~60_combout\ = \Ram_Control_Inst|ram_nops\(1) $ ((((!\Ram_Control_Inst|Add0~67\)))) -- \Ram_Control_Inst|Add0~62\ = CARRY((!\Ram_Control_Inst|ram_nops\(1) & ((!\Ram_Control_Inst|Add0~67COUT1_82\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "a505", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(1), cin0 => \Ram_Control_Inst|Add0~67\, cin1 => \Ram_Control_Inst|Add0~67COUT1_82\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~60_combout\, cout => \Ram_Control_Inst|Add0~62\); -- Location: LC_X3_Y1_N7 \Ram_Control_Inst|Selector20~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector20~0_combout\ = (\Ram_Control_Inst|ram_nops\(1) & ((\Ram_Control_Inst|ram_state.toggle_OE~regout\) # ((\Ram_Control_Inst|ram_state.ram_read~regout\) # (\Ram_Control_Inst|ram_state.ram_get_data~regout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fe00", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.toggle_OE~regout\, datab => \Ram_Control_Inst|ram_state.ram_read~regout\, datac => \Ram_Control_Inst|ram_state.ram_get_data~regout\, datad => \Ram_Control_Inst|ram_nops\(1), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector20~0_combout\); -- Location: LC_X3_Y2_N9 \Ram_Control_Inst|ram_nops[1]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(1) = DFFEAS((\Ram_Control_Inst|ram_state.auto_refresh~regout\) # ((\Ram_Control_Inst|Selector20~0_combout\) # ((\Ram_Control_Inst|Add0~60_combout\ & \Ram_Control_Inst|Selector7~1_combout\))), GLOBAL(\Clk~combout\), -- GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "fefa", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datab => \Ram_Control_Inst|Add0~60_combout\, datac => \Ram_Control_Inst|Selector20~0_combout\, datad => \Ram_Control_Inst|Selector7~1_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(1)); -- Location: LC_X4_Y2_N2 \Ram_Control_Inst|Selector19~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector19~0_combout\ = (\Ram_Control_Inst|ram_state.auto_refresh~regout\) # (((!\Ram_Control_Inst|WideOr10~0\ & \Ram_Control_Inst|ram_nops\(2))) # (!\Ram_Control_Inst|ram_state.init~regout\)) -- pragma translate_off GENERIC MAP ( lut_mask => "bfbb", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datab => \Ram_Control_Inst|ram_state.init~regout\, datac => \Ram_Control_Inst|WideOr10~0\, datad => \Ram_Control_Inst|ram_nops\(2), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector19~0_combout\); -- Location: LC_X4_Y2_N5 \Ram_Control_Inst|Add0~55\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~55_combout\ = (\Ram_Control_Inst|ram_nops\(2) $ ((\Ram_Control_Inst|Add0~62\))) -- \Ram_Control_Inst|Add0~57\ = CARRY(((\Ram_Control_Inst|ram_nops\(2)) # (!\Ram_Control_Inst|Add0~62\))) -- \Ram_Control_Inst|Add0~57COUT1_84\ = CARRY(((\Ram_Control_Inst|ram_nops\(2)) # (!\Ram_Control_Inst|Add0~62\))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "3ccf", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(2), cin => \Ram_Control_Inst|Add0~62\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~55_combout\, cout0 => \Ram_Control_Inst|Add0~57\, cout1 => \Ram_Control_Inst|Add0~57COUT1_84\); -- Location: LC_X4_Y2_N1 \Ram_Control_Inst|ram_nops[2]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(2) = DFFEAS((\Ram_Control_Inst|Selector19~0_combout\) # ((\Ram_Control_Inst|ram_state.nop~regout\ & (\Ram_Control_Inst|Add0~55_combout\ & !\Ram_Control_Inst|Equal0~4_combout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), -- , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ccec", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.nop~regout\, datab => \Ram_Control_Inst|Selector19~0_combout\, datac => \Ram_Control_Inst|Add0~55_combout\, datad => \Ram_Control_Inst|Equal0~4_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(2)); -- Location: LC_X4_Y2_N6 \Ram_Control_Inst|Add0~50\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~50_combout\ = \Ram_Control_Inst|ram_nops\(3) $ ((((!(!\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~57\) # (\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~57COUT1_84\))))) -- \Ram_Control_Inst|Add0~52\ = CARRY((!\Ram_Control_Inst|ram_nops\(3) & ((!\Ram_Control_Inst|Add0~57\)))) -- \Ram_Control_Inst|Add0~52COUT1_86\ = CARRY((!\Ram_Control_Inst|ram_nops\(3) & ((!\Ram_Control_Inst|Add0~57COUT1_84\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "a505", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(3), cin => \Ram_Control_Inst|Add0~62\, cin0 => \Ram_Control_Inst|Add0~57\, cin1 => \Ram_Control_Inst|Add0~57COUT1_84\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~50_combout\, cout0 => \Ram_Control_Inst|Add0~52\, cout1 => \Ram_Control_Inst|Add0~52COUT1_86\); -- Location: LC_X5_Y2_N7 \Ram_Control_Inst|ram_nops[3]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(3) = DFFEAS((\Ram_Control_Inst|ram_nops\(3) & (((\Ram_Control_Inst|Add0~50_combout\ & \Ram_Control_Inst|Selector7~1_combout\)) # (!\Ram_Control_Inst|WideOr10~0\))) # (!\Ram_Control_Inst|ram_nops\(3) & -- (\Ram_Control_Inst|Add0~50_combout\ & (\Ram_Control_Inst|Selector7~1_combout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "c0ea", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_nops\(3), datab => \Ram_Control_Inst|Add0~50_combout\, datac => \Ram_Control_Inst|Selector7~1_combout\, datad => \Ram_Control_Inst|WideOr10~0\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(3)); -- Location: LC_X4_Y2_N7 \Ram_Control_Inst|Add0~45\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~45_combout\ = (\Ram_Control_Inst|ram_nops\(4) $ (((!\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~52\) # (\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~52COUT1_86\)))) -- \Ram_Control_Inst|Add0~47\ = CARRY(((\Ram_Control_Inst|ram_nops\(4)) # (!\Ram_Control_Inst|Add0~52\))) -- \Ram_Control_Inst|Add0~47COUT1_88\ = CARRY(((\Ram_Control_Inst|ram_nops\(4)) # (!\Ram_Control_Inst|Add0~52COUT1_86\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "3ccf", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(4), cin => \Ram_Control_Inst|Add0~62\, cin0 => \Ram_Control_Inst|Add0~52\, cin1 => \Ram_Control_Inst|Add0~52COUT1_86\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~45_combout\, cout0 => \Ram_Control_Inst|Add0~47\, cout1 => \Ram_Control_Inst|Add0~47COUT1_88\); -- Location: LC_X7_Y2_N8 \Ram_Control_Inst|ram_nops[7]~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops[7]~0_combout\ = ((\Ram_Control_Inst|WideOr10~0\ & ((!\Ram_Control_Inst|Equal0~4_combout\) # (!\Ram_Control_Inst|ram_state.nop~regout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "30f0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_state.nop~regout\, datac => \Ram_Control_Inst|WideOr10~0\, datad => \Ram_Control_Inst|Equal0~4_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|ram_nops[7]~0_combout\); -- Location: LC_X7_Y2_N7 \Ram_Control_Inst|ram_nops[4]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(4) = DFFEAS((((\Ram_Control_Inst|Add0~45_combout\ & \Ram_Control_Inst|WideOr16~combout\))) # (!\Ram_Control_Inst|ram_state.init~regout\), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , -- \Ram_Control_Inst|ram_nops[7]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f555", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.init~regout\, datac => \Ram_Control_Inst|Add0~45_combout\, datad => \Ram_Control_Inst|WideOr16~combout\, aclr => \ALT_INV_ResetN~combout\, ena => \Ram_Control_Inst|ram_nops[7]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(4)); -- Location: LC_X4_Y2_N8 \Ram_Control_Inst|Add0~40\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~40_combout\ = (\Ram_Control_Inst|ram_nops\(5) $ ((!(!\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~47\) # (\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~47COUT1_88\)))) -- \Ram_Control_Inst|Add0~42\ = CARRY(((!\Ram_Control_Inst|ram_nops\(5) & !\Ram_Control_Inst|Add0~47\))) -- \Ram_Control_Inst|Add0~42COUT1_90\ = CARRY(((!\Ram_Control_Inst|ram_nops\(5) & !\Ram_Control_Inst|Add0~47COUT1_88\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c303", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(5), cin => \Ram_Control_Inst|Add0~62\, cin0 => \Ram_Control_Inst|Add0~47\, cin1 => \Ram_Control_Inst|Add0~47COUT1_88\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~40_combout\, cout0 => \Ram_Control_Inst|Add0~42\, cout1 => \Ram_Control_Inst|Add0~42COUT1_90\); -- Location: LC_X4_Y2_N0 \Ram_Control_Inst|ram_nops[5]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(5) = DFFEAS((\Ram_Control_Inst|Add0~40_combout\ & ((\Ram_Control_Inst|Selector7~1_combout\) # ((\Ram_Control_Inst|ram_nops\(5) & !\Ram_Control_Inst|WideOr10~0\)))) # (!\Ram_Control_Inst|Add0~40_combout\ & -- (\Ram_Control_Inst|ram_nops\(5) & (!\Ram_Control_Inst|WideOr10~0\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ae0c", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|Add0~40_combout\, datab => \Ram_Control_Inst|ram_nops\(5), datac => \Ram_Control_Inst|WideOr10~0\, datad => \Ram_Control_Inst|Selector7~1_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(5)); -- Location: LC_X4_Y2_N9 \Ram_Control_Inst|Add0~35\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~35_combout\ = (\Ram_Control_Inst|ram_nops\(6) $ (((!\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~42\) # (\Ram_Control_Inst|Add0~62\ & \Ram_Control_Inst|Add0~42COUT1_90\)))) -- \Ram_Control_Inst|Add0~37\ = CARRY(((\Ram_Control_Inst|ram_nops\(6)) # (!\Ram_Control_Inst|Add0~42COUT1_90\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "3ccf", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(6), cin => \Ram_Control_Inst|Add0~62\, cin0 => \Ram_Control_Inst|Add0~42\, cin1 => \Ram_Control_Inst|Add0~42COUT1_90\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~35_combout\, cout => \Ram_Control_Inst|Add0~37\); -- Location: LC_X7_Y2_N6 \Ram_Control_Inst|ram_nops[6]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(6) = DFFEAS((((\Ram_Control_Inst|WideOr16~combout\ & \Ram_Control_Inst|Add0~35_combout\)) # (!\Ram_Control_Inst|ram_state.init~regout\)), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , -- \Ram_Control_Inst|ram_nops[7]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "cf0f", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|WideOr16~combout\, datac => \Ram_Control_Inst|ram_state.init~regout\, datad => \Ram_Control_Inst|Add0~35_combout\, aclr => \ALT_INV_ResetN~combout\, ena => \Ram_Control_Inst|ram_nops[7]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(6)); -- Location: LC_X5_Y2_N0 \Ram_Control_Inst|Add0~30\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~30_combout\ = (\Ram_Control_Inst|ram_nops\(7) $ ((!\Ram_Control_Inst|Add0~37\))) -- \Ram_Control_Inst|Add0~32\ = CARRY(((!\Ram_Control_Inst|ram_nops\(7) & !\Ram_Control_Inst|Add0~37\))) -- \Ram_Control_Inst|Add0~32COUT1_92\ = CARRY(((!\Ram_Control_Inst|ram_nops\(7) & !\Ram_Control_Inst|Add0~37\))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "c303", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(7), cin => \Ram_Control_Inst|Add0~37\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~30_combout\, cout0 => \Ram_Control_Inst|Add0~32\, cout1 => \Ram_Control_Inst|Add0~32COUT1_92\); -- Location: LC_X6_Y2_N9 \Ram_Control_Inst|ram_nops[7]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(7) = DFFEAS((((\Ram_Control_Inst|WideOr16~combout\ & \Ram_Control_Inst|Add0~30_combout\))) # (!\Ram_Control_Inst|ram_state.init~regout\), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , -- \Ram_Control_Inst|ram_nops[7]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f555", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.init~regout\, datac => \Ram_Control_Inst|WideOr16~combout\, datad => \Ram_Control_Inst|Add0~30_combout\, aclr => \ALT_INV_ResetN~combout\, ena => \Ram_Control_Inst|ram_nops[7]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(7)); -- Location: LC_X5_Y2_N1 \Ram_Control_Inst|Add0~25\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~25_combout\ = (\Ram_Control_Inst|ram_nops\(8) $ (((!\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~32\) # (\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~32COUT1_92\)))) -- \Ram_Control_Inst|Add0~27\ = CARRY(((\Ram_Control_Inst|ram_nops\(8)) # (!\Ram_Control_Inst|Add0~32\))) -- \Ram_Control_Inst|Add0~27COUT1_94\ = CARRY(((\Ram_Control_Inst|ram_nops\(8)) # (!\Ram_Control_Inst|Add0~32COUT1_92\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "3ccf", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(8), cin => \Ram_Control_Inst|Add0~37\, cin0 => \Ram_Control_Inst|Add0~32\, cin1 => \Ram_Control_Inst|Add0~32COUT1_92\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~25_combout\, cout0 => \Ram_Control_Inst|Add0~27\, cout1 => \Ram_Control_Inst|Add0~27COUT1_94\); -- Location: LC_X5_Y2_N9 \Ram_Control_Inst|ram_nops[8]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(8) = DFFEAS((\Ram_Control_Inst|WideOr10~0\ & (((\Ram_Control_Inst|Selector7~1_combout\ & \Ram_Control_Inst|Add0~25_combout\)))) # (!\Ram_Control_Inst|WideOr10~0\ & ((\Ram_Control_Inst|ram_nops\(8)) # -- ((\Ram_Control_Inst|Selector7~1_combout\ & \Ram_Control_Inst|Add0~25_combout\)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f444", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|WideOr10~0\, datab => \Ram_Control_Inst|ram_nops\(8), datac => \Ram_Control_Inst|Selector7~1_combout\, datad => \Ram_Control_Inst|Add0~25_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(8)); -- Location: LC_X5_Y2_N2 \Ram_Control_Inst|Add0~20\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~20_combout\ = \Ram_Control_Inst|ram_nops\(9) $ ((((!(!\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~27\) # (\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~27COUT1_94\))))) -- \Ram_Control_Inst|Add0~22\ = CARRY((!\Ram_Control_Inst|ram_nops\(9) & ((!\Ram_Control_Inst|Add0~27\)))) -- \Ram_Control_Inst|Add0~22COUT1_96\ = CARRY((!\Ram_Control_Inst|ram_nops\(9) & ((!\Ram_Control_Inst|Add0~27COUT1_94\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "a505", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(9), cin => \Ram_Control_Inst|Add0~37\, cin0 => \Ram_Control_Inst|Add0~27\, cin1 => \Ram_Control_Inst|Add0~27COUT1_94\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~20_combout\, cout0 => \Ram_Control_Inst|Add0~22\, cout1 => \Ram_Control_Inst|Add0~22COUT1_96\); -- Location: LC_X6_Y2_N6 \Ram_Control_Inst|ram_nops[9]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(9) = DFFEAS((\Ram_Control_Inst|Selector7~1_combout\ & ((\Ram_Control_Inst|Add0~20_combout\) # ((!\Ram_Control_Inst|WideOr10~0\ & \Ram_Control_Inst|ram_nops\(9))))) # (!\Ram_Control_Inst|Selector7~1_combout\ & -- (!\Ram_Control_Inst|WideOr10~0\ & (\Ram_Control_Inst|ram_nops\(9)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ba30", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|Selector7~1_combout\, datab => \Ram_Control_Inst|WideOr10~0\, datac => \Ram_Control_Inst|ram_nops\(9), datad => \Ram_Control_Inst|Add0~20_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(9)); -- Location: LC_X6_Y2_N5 \Ram_Control_Inst|Equal0~1\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Equal0~1_combout\ = (!\Ram_Control_Inst|ram_nops\(9) & (!\Ram_Control_Inst|ram_nops\(7) & (!\Ram_Control_Inst|ram_nops\(6) & !\Ram_Control_Inst|ram_nops\(8)))) -- pragma translate_off GENERIC MAP ( lut_mask => "0001", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(9), datab => \Ram_Control_Inst|ram_nops\(7), datac => \Ram_Control_Inst|ram_nops\(6), datad => \Ram_Control_Inst|ram_nops\(8), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Equal0~1_combout\); -- Location: LC_X5_Y2_N3 \Ram_Control_Inst|Add0~15\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~15_combout\ = (\Ram_Control_Inst|ram_nops\(10) $ (((!\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~22\) # (\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~22COUT1_96\)))) -- \Ram_Control_Inst|Add0~17\ = CARRY(((\Ram_Control_Inst|ram_nops\(10)) # (!\Ram_Control_Inst|Add0~22\))) -- \Ram_Control_Inst|Add0~17COUT1_98\ = CARRY(((\Ram_Control_Inst|ram_nops\(10)) # (!\Ram_Control_Inst|Add0~22COUT1_96\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "3ccf", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(10), cin => \Ram_Control_Inst|Add0~37\, cin0 => \Ram_Control_Inst|Add0~22\, cin1 => \Ram_Control_Inst|Add0~22COUT1_96\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~15_combout\, cout0 => \Ram_Control_Inst|Add0~17\, cout1 => \Ram_Control_Inst|Add0~17COUT1_98\); -- Location: LC_X6_Y2_N4 \Ram_Control_Inst|ram_nops[10]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(10) = DFFEAS((\Ram_Control_Inst|Selector7~1_combout\ & ((\Ram_Control_Inst|Add0~15_combout\) # ((!\Ram_Control_Inst|WideOr10~0\ & \Ram_Control_Inst|ram_nops\(10))))) # (!\Ram_Control_Inst|Selector7~1_combout\ & -- (!\Ram_Control_Inst|WideOr10~0\ & (\Ram_Control_Inst|ram_nops\(10)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ba30", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|Selector7~1_combout\, datab => \Ram_Control_Inst|WideOr10~0\, datac => \Ram_Control_Inst|ram_nops\(10), datad => \Ram_Control_Inst|Add0~15_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(10)); -- Location: LC_X5_Y2_N4 \Ram_Control_Inst|Add0~10\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~10_combout\ = \Ram_Control_Inst|ram_nops\(11) $ ((((!(!\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~17\) # (\Ram_Control_Inst|Add0~37\ & \Ram_Control_Inst|Add0~17COUT1_98\))))) -- \Ram_Control_Inst|Add0~12\ = CARRY((!\Ram_Control_Inst|ram_nops\(11) & ((!\Ram_Control_Inst|Add0~17COUT1_98\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "a505", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(11), cin => \Ram_Control_Inst|Add0~37\, cin0 => \Ram_Control_Inst|Add0~17\, cin1 => \Ram_Control_Inst|Add0~17COUT1_98\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~10_combout\, cout => \Ram_Control_Inst|Add0~12\); -- Location: LC_X5_Y2_N8 \Ram_Control_Inst|ram_nops[11]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(11) = DFFEAS((\Ram_Control_Inst|Add0~10_combout\ & ((\Ram_Control_Inst|Selector7~1_combout\) # ((\Ram_Control_Inst|ram_nops\(11) & !\Ram_Control_Inst|WideOr10~0\)))) # (!\Ram_Control_Inst|Add0~10_combout\ & -- (\Ram_Control_Inst|ram_nops\(11) & ((!\Ram_Control_Inst|WideOr10~0\)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "a0ec", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|Add0~10_combout\, datab => \Ram_Control_Inst|ram_nops\(11), datac => \Ram_Control_Inst|Selector7~1_combout\, datad => \Ram_Control_Inst|WideOr10~0\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(11)); -- Location: LC_X5_Y2_N5 \Ram_Control_Inst|Add0~5\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~5_combout\ = (\Ram_Control_Inst|ram_nops\(12) $ ((\Ram_Control_Inst|Add0~12\))) -- \Ram_Control_Inst|Add0~7\ = CARRY(((\Ram_Control_Inst|ram_nops\(12)) # (!\Ram_Control_Inst|Add0~12\))) -- \Ram_Control_Inst|Add0~7COUT1_100\ = CARRY(((\Ram_Control_Inst|ram_nops\(12)) # (!\Ram_Control_Inst|Add0~12\))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "3ccf", operation_mode => "arithmetic", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_nops\(12), cin => \Ram_Control_Inst|Add0~12\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~5_combout\, cout0 => \Ram_Control_Inst|Add0~7\, cout1 => \Ram_Control_Inst|Add0~7COUT1_100\); -- Location: LC_X6_Y2_N8 \Ram_Control_Inst|ram_nops[12]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(12) = DFFEAS((((\Ram_Control_Inst|WideOr16~combout\ & \Ram_Control_Inst|Add0~5_combout\))) # (!\Ram_Control_Inst|ram_state.init~regout\), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , -- \Ram_Control_Inst|ram_nops[7]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f555", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.init~regout\, datac => \Ram_Control_Inst|WideOr16~combout\, datad => \Ram_Control_Inst|Add0~5_combout\, aclr => \ALT_INV_ResetN~combout\, ena => \Ram_Control_Inst|ram_nops[7]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(12)); -- Location: LC_X5_Y2_N6 \Ram_Control_Inst|Add0~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Add0~0_combout\ = (((!\Ram_Control_Inst|Add0~12\ & \Ram_Control_Inst|Add0~7\) # (\Ram_Control_Inst|Add0~12\ & \Ram_Control_Inst|Add0~7COUT1_100\) $ (!\Ram_Control_Inst|ram_nops\(13)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "f00f", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datad => \Ram_Control_Inst|ram_nops\(13), cin => \Ram_Control_Inst|Add0~12\, cin0 => \Ram_Control_Inst|Add0~7\, cin1 => \Ram_Control_Inst|Add0~7COUT1_100\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Add0~0_combout\); -- Location: LC_X6_Y2_N7 \Ram_Control_Inst|ram_nops[13]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_nops\(13) = DFFEAS(((\Ram_Control_Inst|Add0~0_combout\ & ((\Ram_Control_Inst|WideOr16~combout\)))) # (!\Ram_Control_Inst|ram_state.init~regout\), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , -- \Ram_Control_Inst|ram_nops[7]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "dd55", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.init~regout\, datab => \Ram_Control_Inst|Add0~0_combout\, datad => \Ram_Control_Inst|WideOr16~combout\, aclr => \ALT_INV_ResetN~combout\, ena => \Ram_Control_Inst|ram_nops[7]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_nops\(13)); -- Location: LC_X6_Y2_N0 \Ram_Control_Inst|Equal0~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Equal0~0_combout\ = (!\Ram_Control_Inst|ram_nops\(10) & (!\Ram_Control_Inst|ram_nops\(13) & (!\Ram_Control_Inst|ram_nops\(11) & !\Ram_Control_Inst|ram_nops\(12)))) -- pragma translate_off GENERIC MAP ( lut_mask => "0001", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(10), datab => \Ram_Control_Inst|ram_nops\(13), datac => \Ram_Control_Inst|ram_nops\(11), datad => \Ram_Control_Inst|ram_nops\(12), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Equal0~0_combout\); -- Location: LC_X3_Y2_N6 \Ram_Control_Inst|Equal0~3\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Equal0~3_combout\ = (((!\Ram_Control_Inst|ram_nops\(0) & !\Ram_Control_Inst|ram_nops\(1)))) -- pragma translate_off GENERIC MAP ( lut_mask => "000f", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datac => \Ram_Control_Inst|ram_nops\(0), datad => \Ram_Control_Inst|ram_nops\(1), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Equal0~3_combout\); -- Location: LC_X6_Y2_N1 \Ram_Control_Inst|Equal0~2\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Equal0~2_combout\ = (!\Ram_Control_Inst|ram_nops\(4) & (!\Ram_Control_Inst|ram_nops\(3) & (!\Ram_Control_Inst|ram_nops\(5) & !\Ram_Control_Inst|ram_nops\(2)))) -- pragma translate_off GENERIC MAP ( lut_mask => "0001", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_nops\(4), datab => \Ram_Control_Inst|ram_nops\(3), datac => \Ram_Control_Inst|ram_nops\(5), datad => \Ram_Control_Inst|ram_nops\(2), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Equal0~2_combout\); -- Location: LC_X6_Y2_N2 \Ram_Control_Inst|Equal0~4\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Equal0~4_combout\ = (\Ram_Control_Inst|Equal0~1_combout\ & (\Ram_Control_Inst|Equal0~0_combout\ & (\Ram_Control_Inst|Equal0~3_combout\ & \Ram_Control_Inst|Equal0~2_combout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "8000", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|Equal0~1_combout\, datab => \Ram_Control_Inst|Equal0~0_combout\, datac => \Ram_Control_Inst|Equal0~3_combout\, datad => \Ram_Control_Inst|Equal0~2_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Equal0~4_combout\); -- Location: LC_X4_Y1_N7 \Ram_Control_Inst|ram_next_state.activate\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_next_state.activate~regout\ = DFFEAS((\Ram_Control_Inst|ram_next_state.activate~regout\ & ((\Ram_Control_Inst|WideOr16~combout\) # ((\Ram_Control_Inst|ram_state.precharge~regout\ & !\Ram_Control_Inst|another_refresh~regout\)))) # -- (!\Ram_Control_Inst|ram_next_state.activate~regout\ & (((\Ram_Control_Inst|ram_state.precharge~regout\ & !\Ram_Control_Inst|another_refresh~regout\)))), GLOBAL(\Clk~combout\), VCC, , GLOBAL(\ResetN~combout\), , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "88f8", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_next_state.activate~regout\, datab => \Ram_Control_Inst|WideOr16~combout\, datac => \Ram_Control_Inst|ram_state.precharge~regout\, datad => \Ram_Control_Inst|another_refresh~regout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_next_state.activate~regout\); -- Location: LC_X3_Y2_N1 \Ram_Control_Inst|ram_state.activate\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.activate~regout\ = DFFEAS((\Ram_Control_Inst|ram_state.nop~regout\ & (\Ram_Control_Inst|Equal0~4_combout\ & (\Ram_Control_Inst|ram_next_state.activate~regout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "8080", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.nop~regout\, datab => \Ram_Control_Inst|Equal0~4_combout\, datac => \Ram_Control_Inst|ram_next_state.activate~regout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.activate~regout\); -- Location: LC_X4_Y1_N5 \Ram_Control_Inst|ram_next_state.ram_read\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_next_state.ram_read~regout\ = DFFEAS((\Ram_Control_Inst|ram_state.activate~regout\) # ((\Ram_Control_Inst|WideOr16~combout\ & (\Ram_Control_Inst|ram_next_state.ram_read~regout\))), GLOBAL(\Clk~combout\), VCC, , -- GLOBAL(\ResetN~combout\), , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "eaea", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.activate~regout\, datab => \Ram_Control_Inst|WideOr16~combout\, datac => \Ram_Control_Inst|ram_next_state.ram_read~regout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_next_state.ram_read~regout\); -- Location: LC_X3_Y1_N2 \Ram_Control_Inst|ram_state.ram_read\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.ram_read~regout\ = DFFEAS(((\Ram_Control_Inst|ram_next_state.ram_read~regout\ & (\Ram_Control_Inst|ram_state.nop~regout\ & \Ram_Control_Inst|Equal0~4_combout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "c000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_next_state.ram_read~regout\, datac => \Ram_Control_Inst|ram_state.nop~regout\, datad => \Ram_Control_Inst|Equal0~4_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.ram_read~regout\); -- Location: LC_X3_Y1_N8 \Ram_Control_Inst|ram_state.toggle_OE\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr10~0\ = ((!\Ram_Control_Inst|ram_state.ram_get_data~regout\ & (!D1_ram_state.toggle_OE & !\Ram_Control_Inst|ram_state.ram_read~regout\))) -- \Ram_Control_Inst|ram_state.toggle_OE~regout\ = DFFEAS(\Ram_Control_Inst|WideOr10~0\, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \Ram_Control_Inst|ram_state.ram_get_data~regout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0003", operation_mode => "normal", output_mode => "reg_and_comb", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.ram_get_data~regout\, datac => \Ram_Control_Inst|ram_state.ram_get_data~regout\, datad => \Ram_Control_Inst|ram_state.ram_read~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr10~0\, regout => \Ram_Control_Inst|ram_state.toggle_OE~regout\); -- Location: LC_X3_Y1_N0 \Ram_Control_Inst|ram_state.nop\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.nop~regout\ = DFFEAS(((\Ram_Control_Inst|ram_state.nop~regout\ & ((!\Ram_Control_Inst|Equal0~4_combout\))) # (!\Ram_Control_Inst|ram_state.nop~regout\ & (\Ram_Control_Inst|WideOr10~0\))), GLOBAL(\Clk~combout\), -- GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "0cfc", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|WideOr10~0\, datac => \Ram_Control_Inst|ram_state.nop~regout\, datad => \Ram_Control_Inst|Equal0~4_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.nop~regout\); -- Location: LC_X2_Y3_N5 \Ram_Control_Inst|ram_state.nop_dqm_down\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux10~0\ = ((!\Ram_Control_Inst|ram_state.ram_write~regout\ & (!D1_ram_state.nop_dqm_down & !\Ram_Control_Inst|ram_state.toggle_OE~regout\))) -- \Ram_Control_Inst|ram_state.nop_dqm_down~regout\ = DFFEAS(\AD_DA_Inst|Mux10~0\, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \Ram_Control_Inst|ram_state.ram_read~regout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0003", operation_mode => "normal", output_mode => "reg_and_comb", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.ram_write~regout\, datac => \Ram_Control_Inst|ram_state.ram_read~regout\, datad => \Ram_Control_Inst|ram_state.toggle_OE~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux10~0\, regout => \Ram_Control_Inst|ram_state.nop_dqm_down~regout\); -- Location: LC_X3_Y1_N9 \Ram_Control_Inst|ram_next_state.ram_get_data\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_next_state.ram_get_data~regout\ = DFFEAS(((\Ram_Control_Inst|ram_state.nop_dqm_down~regout\) # ((\Ram_Control_Inst|WideOr16~combout\ & \Ram_Control_Inst|ram_next_state.ram_get_data~regout\))), GLOBAL(\Clk~combout\), VCC, , -- GLOBAL(\ResetN~combout\), , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff88", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|WideOr16~combout\, datab => \Ram_Control_Inst|ram_next_state.ram_get_data~regout\, datad => \Ram_Control_Inst|ram_state.nop_dqm_down~regout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_next_state.ram_get_data~regout\); -- Location: LC_X3_Y1_N1 \Ram_Control_Inst|ram_state.ram_get_data\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|ram_state.ram_get_data~regout\ = DFFEAS(((\Ram_Control_Inst|ram_state.nop~regout\ & (\Ram_Control_Inst|ram_next_state.ram_get_data~regout\ & \Ram_Control_Inst|Equal0~4_combout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , -- , ) -- pragma translate_off GENERIC MAP ( lut_mask => "c000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.nop~regout\, datac => \Ram_Control_Inst|ram_next_state.ram_get_data~regout\, datad => \Ram_Control_Inst|Equal0~4_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|ram_state.ram_get_data~regout\); -- Location: LC_X2_Y1_N5 \Ram_Control_Inst|ram_state.ram_write\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr30~0\ = (((!D1_ram_state.ram_write & !\Ram_Control_Inst|ram_state.set_mode_register~regout\))) -- \Ram_Control_Inst|ram_state.ram_write~regout\ = DFFEAS(\Ram_Control_Inst|WideOr30~0\, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \Ram_Control_Inst|ram_state.toggle_OE~regout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "000f", operation_mode => "normal", output_mode => "reg_and_comb", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Ram_Control_Inst|ram_state.toggle_OE~regout\, datad => \Ram_Control_Inst|ram_state.set_mode_register~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr30~0\, regout => \Ram_Control_Inst|ram_state.ram_write~regout\); -- Location: LC_X2_Y1_N6 \Ram_Control_Inst|WideOr30~1\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr30~1_combout\ = (\Ram_Control_Inst|ram_state.ram_get_data~regout\) # ((\Ram_Control_Inst|ram_state.ram_read~regout\) # ((\Ram_Control_Inst|ram_state.precharge~regout\) # (!\Ram_Control_Inst|WideOr30~0\))) -- pragma translate_off GENERIC MAP ( lut_mask => "feff", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.ram_get_data~regout\, datab => \Ram_Control_Inst|ram_state.ram_read~regout\, datac => \Ram_Control_Inst|ram_state.precharge~regout\, datad => \Ram_Control_Inst|WideOr30~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr30~1_combout\); -- Location: LC_X2_Y3_N4 \Ram_Control_Inst|WideOr31~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr31~0_combout\ = (\Ram_Control_Inst|ram_state.nop_dqm_down~regout\) # (((\Ram_Control_Inst|ram_state.ram_get_data~regout\) # (!\Ram_Control_Inst|Selector30~0_combout\)) # (!\Ram_Control_Inst|ram_state.init~regout\)) -- pragma translate_off GENERIC MAP ( lut_mask => "fbff", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.nop_dqm_down~regout\, datab => \Ram_Control_Inst|ram_state.init~regout\, datac => \Ram_Control_Inst|ram_state.ram_get_data~regout\, datad => \Ram_Control_Inst|Selector30~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr31~0_combout\); -- Location: LC_X2_Y3_N9 \Ram_Control_Inst|WideOr29~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr29~0_combout\ = (\Ram_Control_Inst|ram_state.ram_get_data~regout\) # ((\Ram_Control_Inst|ram_state.ram_read~regout\) # ((\Ram_Control_Inst|ram_state.auto_refresh~regout\) # (\Ram_Control_Inst|ram_state.activate~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "fffe", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.ram_get_data~regout\, datab => \Ram_Control_Inst|ram_state.ram_read~regout\, datac => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datad => \Ram_Control_Inst|ram_state.activate~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr29~0_combout\); -- Location: LC_X2_Y3_N3 \rtl~0\ : maxii_lcell -- Equation(s): -- \rtl~0_combout\ = LCELL((\AD_DA_Inst|Mux10~0\ & (\Ram_Control_Inst|WideOr30~1_combout\ & (\Ram_Control_Inst|WideOr31~0_combout\ & !\Ram_Control_Inst|WideOr29~0_combout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "0080", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \AD_DA_Inst|Mux10~0\, datab => \Ram_Control_Inst|WideOr30~1_combout\, datac => \Ram_Control_Inst|WideOr31~0_combout\, datad => \Ram_Control_Inst|WideOr29~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \rtl~0_combout\); -- Location: PIN_69, I/O Standard: 3.3-V LVTTL, Current Strength: Default \MOSI~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_MOSI, combout => \MOSI~combout\); -- Location: LC_X7_Y3_N5 \RX_TX_Inst|MOSI_f\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|MOSI_f~regout\ = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \MOSI~combout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \MOSI~combout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|MOSI_f~regout\); -- Location: LC_X7_Y3_N6 \RX_TX_Inst|MOSI_ff\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|MOSI_ff~regout\ = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \RX_TX_Inst|MOSI_f~regout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|MOSI_f~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|MOSI_ff~regout\); -- Location: PIN_71, I/O Standard: 3.3-V LVTTL, Current Strength: Default \SCK~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_SCK, combout => \SCK~combout\); -- Location: LC_X6_Y3_N5 \RX_TX_Inst|SCK_f\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|SCK_f~regout\ = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \SCK~combout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \SCK~combout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|SCK_f~regout\); -- Location: LC_X6_Y3_N2 \RX_TX_Inst|SCK_ff\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|SCK_ff~regout\ = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \RX_TX_Inst|SCK_f~regout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|SCK_f~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|SCK_ff~regout\); -- Location: PIN_72, I/O Standard: 3.3-V LVTTL, Current Strength: Default \CSn~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_CSn, combout => \CSn~combout\); -- Location: LC_X6_Y3_N7 \RX_TX_Inst|CSn_f\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|CSn_f~regout\ = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \CSn~combout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \CSn~combout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|CSn_f~regout\); -- Location: LC_X6_Y3_N9 \RX_TX_Inst|CSn_ff\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|CSn_ff~regout\ = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , \RX_TX_Inst|CSn_f~regout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|CSn_f~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|CSn_ff~regout\); -- Location: LC_X6_Y3_N8 \RX_TX_Inst|SCKIntOld\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf[7]~0\ = ((\RX_TX_Inst|SCK_ff~regout\ & (!E1_SCKIntOld & !\RX_TX_Inst|CSn_ff~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "000c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \RX_TX_Inst|SCK_ff~regout\, datac => \RX_TX_Inst|SCK_ff~regout\, datad => \RX_TX_Inst|CSn_ff~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, combout => \RX_TX_Inst|Rx_Buf[7]~0\, regout => \RX_TX_Inst|SCKIntOld~regout\); -- Location: LC_X7_Y3_N1 \RX_TX_Inst|Rx_Buf[0]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(0) = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, \RX_TX_Inst|MOSI_ff~regout\, , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|MOSI_ff~regout\, aclr => \ALT_INV_ResetN~combout\, sload => VCC, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(0)); -- Location: LC_X7_Y3_N8 \RX_TX_Inst|Rx_Buf[1]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(1) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(0)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(0), aclr => \ALT_INV_ResetN~combout\, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(1)); -- Location: LC_X7_Y3_N9 \RX_TX_Inst|Rx_Buf[2]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(2) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(1)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(1), aclr => \ALT_INV_ResetN~combout\, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(2)); -- Location: LC_X7_Y3_N4 \RX_TX_Inst|Rx_Buf[3]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(3) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(2)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(2), aclr => \ALT_INV_ResetN~combout\, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(3)); -- Location: LC_X5_Y3_N4 \RX_TX_Inst|Rx_Buf[4]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(4) = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, \RX_TX_Inst|Rx_Buf\(3), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|Rx_Buf\(3), aclr => \ALT_INV_ResetN~combout\, sload => VCC, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(4)); -- Location: LC_X5_Y3_N9 \RX_TX_Inst|Rx_Buf[5]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(5) = DFFEAS(GND, GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, \RX_TX_Inst|Rx_Buf\(4), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|Rx_Buf\(4), aclr => \ALT_INV_ResetN~combout\, sload => VCC, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(5)); -- Location: LC_X5_Y3_N8 \RX_TX_Inst|Rx_Buf[6]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(6) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(5)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(5), aclr => \ALT_INV_ResetN~combout\, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(6)); -- Location: LC_X5_Y3_N3 \RX_TX_Inst|Rx_Buf[7]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Rx_Buf\(7) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(6)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \RX_TX_Inst|Rx_Buf[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(6), aclr => \ALT_INV_ResetN~combout\, ena => \RX_TX_Inst|Rx_Buf[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Rx_Buf\(7)); -- Location: LC_X6_Y3_N0 \RX_TX_Inst|CSIntOld\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data[7]~0\ = ((GLOBAL(\ResetN~combout\) & (!E1_CSIntOld & \RX_TX_Inst|CSn_ff~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "0c00", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \ResetN~combout\, datac => \RX_TX_Inst|CSn_ff~regout\, datad => \RX_TX_Inst|CSn_ff~regout\, aclr => GND, sload => VCC, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \RX_TX_Inst|Receive_Data[7]~0\, regout => \RX_TX_Inst|CSIntOld~regout\); -- Location: LC_X5_Y3_N1 \RX_TX_Inst|Receive_Data[7]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(7) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(7)))), GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(7), aclr => GND, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(7)); -- Location: LC_X7_Y4_N0 \Address_Counter_Inst|frame_count[7]~2\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count[7]~2_combout\ = (((\Address_Counter_Inst|counter_did_reset~regout\) # (!GLOBAL(\ResetN~combout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "ff0f", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datac => \ResetN~combout\, datad => \Address_Counter_Inst|counter_did_reset~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|frame_count[7]~2_combout\); -- Location: LC_X7_Y4_N8 \Address_Counter_Inst|frame_count[0]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(0) = DFFEAS((((!\Address_Counter_Inst|frame_count\(0)))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "00ff", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, datad => \Address_Counter_Inst|frame_count\(0), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(0)); -- Location: LC_X7_Y4_N1 \Address_Counter_Inst|frame_count[1]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(1) = DFFEAS(\Address_Counter_Inst|frame_count\(0) $ ((\Address_Counter_Inst|frame_count\(1))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- \Address_Counter_Inst|frame_count[1]~14\ = CARRY((\Address_Counter_Inst|frame_count\(0) & (\Address_Counter_Inst|frame_count\(1)))) -- \Address_Counter_Inst|frame_count[1]~14COUT1_23\ = CARRY((\Address_Counter_Inst|frame_count\(0) & (\Address_Counter_Inst|frame_count\(1)))) -- pragma translate_off GENERIC MAP ( lut_mask => "6688", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, dataa => \Address_Counter_Inst|frame_count\(0), datab => \Address_Counter_Inst|frame_count\(1), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(1), cout0 => \Address_Counter_Inst|frame_count[1]~14\, cout1 => \Address_Counter_Inst|frame_count[1]~14COUT1_23\); -- Location: LC_X7_Y4_N2 \Address_Counter_Inst|frame_count[2]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(2) = DFFEAS((\Address_Counter_Inst|frame_count\(2) $ ((\Address_Counter_Inst|frame_count[1]~14\))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- \Address_Counter_Inst|frame_count[2]~12\ = CARRY(((!\Address_Counter_Inst|frame_count[1]~14\) # (!\Address_Counter_Inst|frame_count\(2)))) -- \Address_Counter_Inst|frame_count[2]~12COUT1_25\ = CARRY(((!\Address_Counter_Inst|frame_count[1]~14COUT1_23\) # (!\Address_Counter_Inst|frame_count\(2)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "3c3f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, datab => \Address_Counter_Inst|frame_count\(2), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, cin0 => \Address_Counter_Inst|frame_count[1]~14\, cin1 => \Address_Counter_Inst|frame_count[1]~14COUT1_23\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(2), cout0 => \Address_Counter_Inst|frame_count[2]~12\, cout1 => \Address_Counter_Inst|frame_count[2]~12COUT1_25\); -- Location: LC_X7_Y4_N3 \Address_Counter_Inst|frame_count[3]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(3) = DFFEAS(\Address_Counter_Inst|frame_count\(3) $ ((((!\Address_Counter_Inst|frame_count[2]~12\)))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- \Address_Counter_Inst|frame_count[3]~10\ = CARRY((\Address_Counter_Inst|frame_count\(3) & ((!\Address_Counter_Inst|frame_count[2]~12\)))) -- \Address_Counter_Inst|frame_count[3]~10COUT1_27\ = CARRY((\Address_Counter_Inst|frame_count\(3) & ((!\Address_Counter_Inst|frame_count[2]~12COUT1_25\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "a50a", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, dataa => \Address_Counter_Inst|frame_count\(3), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, cin0 => \Address_Counter_Inst|frame_count[2]~12\, cin1 => \Address_Counter_Inst|frame_count[2]~12COUT1_25\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(3), cout0 => \Address_Counter_Inst|frame_count[3]~10\, cout1 => \Address_Counter_Inst|frame_count[3]~10COUT1_27\); -- Location: LC_X7_Y4_N4 \Address_Counter_Inst|frame_count[4]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(4) = DFFEAS(\Address_Counter_Inst|frame_count\(4) $ ((((\Address_Counter_Inst|frame_count[3]~10\)))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- \Address_Counter_Inst|frame_count[4]~8\ = CARRY(((!\Address_Counter_Inst|frame_count[3]~10COUT1_27\)) # (!\Address_Counter_Inst|frame_count\(4))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, dataa => \Address_Counter_Inst|frame_count\(4), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, cin0 => \Address_Counter_Inst|frame_count[3]~10\, cin1 => \Address_Counter_Inst|frame_count[3]~10COUT1_27\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(4), cout => \Address_Counter_Inst|frame_count[4]~8\); -- Location: LC_X7_Y4_N5 \Address_Counter_Inst|frame_count[5]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(5) = DFFEAS(\Address_Counter_Inst|frame_count\(5) $ ((((!\Address_Counter_Inst|frame_count[4]~8\)))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- \Address_Counter_Inst|frame_count[5]~6\ = CARRY((\Address_Counter_Inst|frame_count\(5) & ((!\Address_Counter_Inst|frame_count[4]~8\)))) -- \Address_Counter_Inst|frame_count[5]~6COUT1_29\ = CARRY((\Address_Counter_Inst|frame_count\(5) & ((!\Address_Counter_Inst|frame_count[4]~8\)))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "a50a", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, dataa => \Address_Counter_Inst|frame_count\(5), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, cin => \Address_Counter_Inst|frame_count[4]~8\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(5), cout0 => \Address_Counter_Inst|frame_count[5]~6\, cout1 => \Address_Counter_Inst|frame_count[5]~6COUT1_29\); -- Location: LC_X7_Y4_N6 \Address_Counter_Inst|frame_count[6]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(6) = DFFEAS(\Address_Counter_Inst|frame_count\(6) $ (((((!\Address_Counter_Inst|frame_count[4]~8\ & \Address_Counter_Inst|frame_count[5]~6\) # (\Address_Counter_Inst|frame_count[4]~8\ & -- \Address_Counter_Inst|frame_count[5]~6COUT1_29\))))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- \Address_Counter_Inst|frame_count[6]~4\ = CARRY(((!\Address_Counter_Inst|frame_count[5]~6\)) # (!\Address_Counter_Inst|frame_count\(6))) -- \Address_Counter_Inst|frame_count[6]~4COUT1_31\ = CARRY(((!\Address_Counter_Inst|frame_count[5]~6COUT1_29\)) # (!\Address_Counter_Inst|frame_count\(6))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, dataa => \Address_Counter_Inst|frame_count\(6), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, cin => \Address_Counter_Inst|frame_count[4]~8\, cin0 => \Address_Counter_Inst|frame_count[5]~6\, cin1 => \Address_Counter_Inst|frame_count[5]~6COUT1_29\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(6), cout0 => \Address_Counter_Inst|frame_count[6]~4\, cout1 => \Address_Counter_Inst|frame_count[6]~4COUT1_31\); -- Location: LC_X7_Y4_N7 \Address_Counter_Inst|frame_count[7]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|frame_count\(7) = DFFEAS(\Address_Counter_Inst|frame_count\(7) $ ((((!(!\Address_Counter_Inst|frame_count[4]~8\ & \Address_Counter_Inst|frame_count[6]~4\) # (\Address_Counter_Inst|frame_count[4]~8\ & -- \Address_Counter_Inst|frame_count[6]~4COUT1_31\))))), \V_Sync~combout\, !\Address_Counter_Inst|frame_count[7]~2_combout\, , , , , , ) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "a5a5", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, dataa => \Address_Counter_Inst|frame_count\(7), aclr => \Address_Counter_Inst|frame_count[7]~2_combout\, cin => \Address_Counter_Inst|frame_count[4]~8\, cin0 => \Address_Counter_Inst|frame_count[6]~4\, cin1 => \Address_Counter_Inst|frame_count[6]~4COUT1_31\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|frame_count\(7)); -- Location: LC_X5_Y3_N6 \RX_TX_Inst|Receive_Data[4]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(4) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, \RX_TX_Inst|Rx_Buf\(4), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|Rx_Buf\(4), aclr => GND, sload => VCC, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(4)); -- Location: LC_X6_Y4_N9 \RX_TX_Inst|Receive_Data[3]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(3) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, \RX_TX_Inst|Rx_Buf\(3), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|Rx_Buf\(3), aclr => GND, sload => VCC, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(3)); -- Location: LC_X5_Y3_N5 \RX_TX_Inst|Receive_Data[2]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(2) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, \RX_TX_Inst|Rx_Buf\(2), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|Rx_Buf\(2), aclr => GND, sload => VCC, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(2)); -- Location: LC_X5_Y3_N7 \RX_TX_Inst|Receive_Data[1]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(1) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, \RX_TX_Inst|Rx_Buf\(1), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|Rx_Buf\(1), aclr => GND, sload => VCC, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(1)); -- Location: LC_X6_Y4_N8 \RX_TX_Inst|Receive_Data[0]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(0) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, \RX_TX_Inst|Rx_Buf\(0), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \RX_TX_Inst|Rx_Buf\(0), aclr => GND, sload => VCC, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(0)); -- Location: LC_X6_Y4_N0 \Address_Counter_Inst|LessThan0~37\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~37_cout0\ = CARRY((\RX_TX_Inst|Receive_Data\(0) & (!\Address_Counter_Inst|frame_count\(0)))) -- \Address_Counter_Inst|LessThan0~37COUT1_48\ = CARRY((\RX_TX_Inst|Receive_Data\(0) & (!\Address_Counter_Inst|frame_count\(0)))) -- pragma translate_off GENERIC MAP ( lut_mask => "ff22", operation_mode => "arithmetic", output_mode => "none", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \RX_TX_Inst|Receive_Data\(0), datab => \Address_Counter_Inst|frame_count\(0), devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~35\, cout0 => \Address_Counter_Inst|LessThan0~37_cout0\, cout1 => \Address_Counter_Inst|LessThan0~37COUT1_48\); -- Location: LC_X6_Y4_N1 \Address_Counter_Inst|LessThan0~32\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~32_cout0\ = CARRY((\Address_Counter_Inst|frame_count\(1) & ((!\Address_Counter_Inst|LessThan0~37_cout0\) # (!\RX_TX_Inst|Receive_Data\(1)))) # (!\Address_Counter_Inst|frame_count\(1) & (!\RX_TX_Inst|Receive_Data\(1) & -- !\Address_Counter_Inst|LessThan0~37_cout0\))) -- \Address_Counter_Inst|LessThan0~32COUT1_50\ = CARRY((\Address_Counter_Inst|frame_count\(1) & ((!\Address_Counter_Inst|LessThan0~37COUT1_48\) # (!\RX_TX_Inst|Receive_Data\(1)))) # (!\Address_Counter_Inst|frame_count\(1) & (!\RX_TX_Inst|Receive_Data\(1) & -- !\Address_Counter_Inst|LessThan0~37COUT1_48\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "ff2b", operation_mode => "arithmetic", output_mode => "none", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Address_Counter_Inst|frame_count\(1), datab => \RX_TX_Inst|Receive_Data\(1), cin0 => \Address_Counter_Inst|LessThan0~37_cout0\, cin1 => \Address_Counter_Inst|LessThan0~37COUT1_48\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~30\, cout0 => \Address_Counter_Inst|LessThan0~32_cout0\, cout1 => \Address_Counter_Inst|LessThan0~32COUT1_50\); -- Location: LC_X6_Y4_N2 \Address_Counter_Inst|LessThan0~27\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~27_cout0\ = CARRY((\RX_TX_Inst|Receive_Data\(2) & ((!\Address_Counter_Inst|LessThan0~32_cout0\) # (!\Address_Counter_Inst|frame_count\(2)))) # (!\RX_TX_Inst|Receive_Data\(2) & (!\Address_Counter_Inst|frame_count\(2) & -- !\Address_Counter_Inst|LessThan0~32_cout0\))) -- \Address_Counter_Inst|LessThan0~27COUT1_52\ = CARRY((\RX_TX_Inst|Receive_Data\(2) & ((!\Address_Counter_Inst|LessThan0~32COUT1_50\) # (!\Address_Counter_Inst|frame_count\(2)))) # (!\RX_TX_Inst|Receive_Data\(2) & (!\Address_Counter_Inst|frame_count\(2) & -- !\Address_Counter_Inst|LessThan0~32COUT1_50\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "ff2b", operation_mode => "arithmetic", output_mode => "none", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \RX_TX_Inst|Receive_Data\(2), datab => \Address_Counter_Inst|frame_count\(2), cin0 => \Address_Counter_Inst|LessThan0~32_cout0\, cin1 => \Address_Counter_Inst|LessThan0~32COUT1_50\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~25\, cout0 => \Address_Counter_Inst|LessThan0~27_cout0\, cout1 => \Address_Counter_Inst|LessThan0~27COUT1_52\); -- Location: LC_X6_Y4_N3 \Address_Counter_Inst|LessThan0~22\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~22_cout0\ = CARRY((\Address_Counter_Inst|frame_count\(3) & ((!\Address_Counter_Inst|LessThan0~27_cout0\) # (!\RX_TX_Inst|Receive_Data\(3)))) # (!\Address_Counter_Inst|frame_count\(3) & (!\RX_TX_Inst|Receive_Data\(3) & -- !\Address_Counter_Inst|LessThan0~27_cout0\))) -- \Address_Counter_Inst|LessThan0~22COUT1_54\ = CARRY((\Address_Counter_Inst|frame_count\(3) & ((!\Address_Counter_Inst|LessThan0~27COUT1_52\) # (!\RX_TX_Inst|Receive_Data\(3)))) # (!\Address_Counter_Inst|frame_count\(3) & (!\RX_TX_Inst|Receive_Data\(3) & -- !\Address_Counter_Inst|LessThan0~27COUT1_52\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "ff2b", operation_mode => "arithmetic", output_mode => "none", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Address_Counter_Inst|frame_count\(3), datab => \RX_TX_Inst|Receive_Data\(3), cin0 => \Address_Counter_Inst|LessThan0~27_cout0\, cin1 => \Address_Counter_Inst|LessThan0~27COUT1_52\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~20\, cout0 => \Address_Counter_Inst|LessThan0~22_cout0\, cout1 => \Address_Counter_Inst|LessThan0~22COUT1_54\); -- Location: LC_X6_Y4_N4 \Address_Counter_Inst|LessThan0~17\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~17_cout\ = CARRY((\RX_TX_Inst|Receive_Data\(4) & ((!\Address_Counter_Inst|LessThan0~22COUT1_54\) # (!\Address_Counter_Inst|frame_count\(4)))) # (!\RX_TX_Inst|Receive_Data\(4) & (!\Address_Counter_Inst|frame_count\(4) & -- !\Address_Counter_Inst|LessThan0~22COUT1_54\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "ff2b", operation_mode => "arithmetic", output_mode => "none", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \RX_TX_Inst|Receive_Data\(4), datab => \Address_Counter_Inst|frame_count\(4), cin0 => \Address_Counter_Inst|LessThan0~22_cout0\, cin1 => \Address_Counter_Inst|LessThan0~22COUT1_54\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~15\, cout => \Address_Counter_Inst|LessThan0~17_cout\); -- Location: LC_X5_Y3_N2 \RX_TX_Inst|Receive_Data[6]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(6) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(6)))), GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(6), aclr => GND, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(6)); -- Location: LC_X5_Y3_N0 \RX_TX_Inst|Receive_Data[5]\ : maxii_lcell -- Equation(s): -- \RX_TX_Inst|Receive_Data\(5) = DFFEAS((((\RX_TX_Inst|Rx_Buf\(5)))), GLOBAL(\Clk~combout\), VCC, , \RX_TX_Inst|Receive_Data[7]~0\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \RX_TX_Inst|Rx_Buf\(5), aclr => GND, ena => \RX_TX_Inst|Receive_Data[7]~0\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \RX_TX_Inst|Receive_Data\(5)); -- Location: LC_X6_Y4_N5 \Address_Counter_Inst|LessThan0~12\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~12_cout0\ = CARRY((\RX_TX_Inst|Receive_Data\(5) & (\Address_Counter_Inst|frame_count\(5) & !\Address_Counter_Inst|LessThan0~17_cout\)) # (!\RX_TX_Inst|Receive_Data\(5) & ((\Address_Counter_Inst|frame_count\(5)) # -- (!\Address_Counter_Inst|LessThan0~17_cout\)))) -- \Address_Counter_Inst|LessThan0~12COUT1_56\ = CARRY((\RX_TX_Inst|Receive_Data\(5) & (\Address_Counter_Inst|frame_count\(5) & !\Address_Counter_Inst|LessThan0~17_cout\)) # (!\RX_TX_Inst|Receive_Data\(5) & ((\Address_Counter_Inst|frame_count\(5)) # -- (!\Address_Counter_Inst|LessThan0~17_cout\)))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "ff4d", operation_mode => "arithmetic", output_mode => "none", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \RX_TX_Inst|Receive_Data\(5), datab => \Address_Counter_Inst|frame_count\(5), cin => \Address_Counter_Inst|LessThan0~17_cout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~10\, cout0 => \Address_Counter_Inst|LessThan0~12_cout0\, cout1 => \Address_Counter_Inst|LessThan0~12COUT1_56\); -- Location: LC_X6_Y4_N6 \Address_Counter_Inst|LessThan0~7\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~7_cout0\ = CARRY((\Address_Counter_Inst|frame_count\(6) & (\RX_TX_Inst|Receive_Data\(6) & !\Address_Counter_Inst|LessThan0~12_cout0\)) # (!\Address_Counter_Inst|frame_count\(6) & ((\RX_TX_Inst|Receive_Data\(6)) # -- (!\Address_Counter_Inst|LessThan0~12_cout0\)))) -- \Address_Counter_Inst|LessThan0~7COUT1_58\ = CARRY((\Address_Counter_Inst|frame_count\(6) & (\RX_TX_Inst|Receive_Data\(6) & !\Address_Counter_Inst|LessThan0~12COUT1_56\)) # (!\Address_Counter_Inst|frame_count\(6) & ((\RX_TX_Inst|Receive_Data\(6)) # -- (!\Address_Counter_Inst|LessThan0~12COUT1_56\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "ff4d", operation_mode => "arithmetic", output_mode => "none", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Address_Counter_Inst|frame_count\(6), datab => \RX_TX_Inst|Receive_Data\(6), cin => \Address_Counter_Inst|LessThan0~17_cout\, cin0 => \Address_Counter_Inst|LessThan0~12_cout0\, cin1 => \Address_Counter_Inst|LessThan0~12COUT1_56\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~5\, cout0 => \Address_Counter_Inst|LessThan0~7_cout0\, cout1 => \Address_Counter_Inst|LessThan0~7COUT1_58\); -- Location: LC_X6_Y4_N7 \Address_Counter_Inst|LessThan0~0\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|LessThan0~0_combout\ = ((\RX_TX_Inst|Receive_Data\(7) & (((!\Address_Counter_Inst|LessThan0~17_cout\ & \Address_Counter_Inst|LessThan0~7_cout0\) # (\Address_Counter_Inst|LessThan0~17_cout\ & -- \Address_Counter_Inst|LessThan0~7COUT1_58\)) # (!\Address_Counter_Inst|frame_count\(7)))) # (!\RX_TX_Inst|Receive_Data\(7) & ((!\Address_Counter_Inst|LessThan0~17_cout\ & \Address_Counter_Inst|LessThan0~7_cout0\) # -- (\Address_Counter_Inst|LessThan0~17_cout\ & \Address_Counter_Inst|LessThan0~7COUT1_58\) & !\Address_Counter_Inst|frame_count\(7)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c0fc", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \RX_TX_Inst|Receive_Data\(7), datad => \Address_Counter_Inst|frame_count\(7), cin => \Address_Counter_Inst|LessThan0~17_cout\, cin0 => \Address_Counter_Inst|LessThan0~7_cout0\, cin1 => \Address_Counter_Inst|LessThan0~7COUT1_58\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Address_Counter_Inst|LessThan0~0_combout\); -- Location: LC_X7_Y4_N9 \Address_Counter_Inst|counter_did_reset\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_did_reset~regout\ = DFFEAS((((!\Address_Counter_Inst|LessThan0~0_combout\))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "00ff", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datad => \Address_Counter_Inst|LessThan0~0_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_did_reset~regout\); -- Location: LC_X2_Y3_N8 \AD_DA_Inst|Mux1~0\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux1~0_combout\ = (\Ram_Control_Inst|WideOr31~0_combout\ & (\AD_DA_Inst|Mux10~0\ & (\Ram_Control_Inst|WideOr29~0_combout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "8080", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|WideOr31~0_combout\, datab => \AD_DA_Inst|Mux10~0\, datac => \Ram_Control_Inst|WideOr29~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux1~0_combout\); -- Location: LC_X2_Y1_N7 \AD_DA_Inst|AD_Clk\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|AD_Clk~combout\ = ((\AD_DA_Inst|Mux1~0_combout\ & ((\Ram_Control_Inst|WideOr30~1_combout\))) # (!\AD_DA_Inst|Mux1~0_combout\ & (\AD_DA_Inst|AD_Clk~combout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc30", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|Mux1~0_combout\, datac => \AD_DA_Inst|AD_Clk~combout\, datad => \Ram_Control_Inst|WideOr30~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|AD_Clk~combout\); -- Location: LC_X2_Y3_N6 \AD_DA_Inst|Mux10~1\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux10~1_combout\ = (\Ram_Control_Inst|WideOr30~1_combout\ & (\Ram_Control_Inst|WideOr29~0_combout\ & (!\Ram_Control_Inst|WideOr31~0_combout\ & \AD_DA_Inst|Mux10~0\))) -- pragma translate_off GENERIC MAP ( lut_mask => "0800", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|WideOr30~1_combout\, datab => \Ram_Control_Inst|WideOr29~0_combout\, datac => \Ram_Control_Inst|WideOr31~0_combout\, datad => \AD_DA_Inst|Mux10~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux10~1_combout\); -- Location: LC_X6_Y1_N3 bypass : maxii_lcell -- Equation(s): -- \bypass~regout\ = DFFEAS((((!\Rec_Button~combout\))), \V_Sync~combout\, GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "00ff", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, datad => \Rec_Button~combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \bypass~regout\); -- Location: PIN_35, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[0]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(0), combout => \AD_Data~combout\(0)); -- Location: LC_X5_Y1_N4 \AD_DA_Inst|ad_data[0]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(0) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_Data~combout\(0))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|ad_data\(0))))) -- pragma translate_off GENERIC MAP ( lut_mask => "cfc0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_Data~combout\(0), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|ad_data\(0), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(0)); -- Location: LC_X5_Y1_N3 \Ram_Control_Inst|load_enable\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|load_enable~regout\ = DFFEAS(((\Ram_Control_Inst|ram_state.ram_get_data~regout\) # ((!\Ram_Control_Inst|ram_state.toggle_OE~regout\ & \Ram_Control_Inst|load_enable~regout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff50", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.toggle_OE~regout\, datac => \Ram_Control_Inst|load_enable~regout\, datad => \Ram_Control_Inst|ram_state.ram_get_data~regout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|load_enable~regout\); -- Location: LC_X5_Y1_N5 \Ram_Control_Inst|Read_Data[0]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux2~0\ = (\bypass~regout\ & (((\AD_DA_Inst|ad_data\(0))))) # (!\bypass~regout\ & (((D1_Read_Data[0])))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa50", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, dataa => \bypass~regout\, datac => \Ram_Data[0]~0\, datad => \AD_DA_Inst|ad_data\(0), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux2~0\, regout => \Ram_Control_Inst|Read_Data\(0)); -- Location: LC_X5_Y1_N6 \AD_DA_Inst|DA_Out[0]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(0) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux2~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(0)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa0a", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \AD_DA_Inst|DA_Out\(0), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux2~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(0)); -- Location: PIN_34, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[1]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(1), combout => \AD_Data~combout\(1)); -- Location: LC_X5_Y1_N7 \AD_DA_Inst|ad_data[1]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(1) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_Data~combout\(1)))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|ad_data\(1)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|ad_data\(1), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_Data~combout\(1), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(1)); -- Location: LC_X5_Y1_N8 \Ram_Control_Inst|Read_Data[1]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux3~0\ = (\bypass~regout\ & (((\AD_DA_Inst|ad_data\(1))))) # (!\bypass~regout\ & (((D1_Read_Data[1])))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa50", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, dataa => \bypass~regout\, datac => \Ram_Data[1]~1\, datad => \AD_DA_Inst|ad_data\(1), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux3~0\, regout => \Ram_Control_Inst|Read_Data\(1)); -- Location: LC_X5_Y1_N9 \AD_DA_Inst|DA_Out[1]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(1) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux3~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(1)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|DA_Out\(1), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux3~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(1)); -- Location: PIN_33, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[2]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(2), combout => \AD_Data~combout\(2)); -- Location: LC_X5_Y1_N2 \AD_DA_Inst|ad_data[2]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(2) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_Data~combout\(2))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|ad_data\(2))))) -- pragma translate_off GENERIC MAP ( lut_mask => "cfc0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_Data~combout\(2), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|ad_data\(2), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(2)); -- Location: LC_X5_Y1_N0 \Ram_Control_Inst|Read_Data[2]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux4~0\ = (\bypass~regout\ & (((\AD_DA_Inst|ad_data\(2))))) # (!\bypass~regout\ & (((D1_Read_Data[2])))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa50", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, dataa => \bypass~regout\, datac => \Ram_Data[2]~2\, datad => \AD_DA_Inst|ad_data\(2), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux4~0\, regout => \Ram_Control_Inst|Read_Data\(2)); -- Location: LC_X5_Y1_N1 \AD_DA_Inst|DA_Out[2]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(2) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux4~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(2)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|DA_Out\(2), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux4~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(2)); -- Location: PIN_30, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[3]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(3), combout => \AD_Data~combout\(3)); -- Location: LC_X6_Y1_N4 \AD_DA_Inst|ad_data[3]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(3) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_Data~combout\(3))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|ad_data\(3))))) -- pragma translate_off GENERIC MAP ( lut_mask => "cfc0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_Data~combout\(3), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|ad_data\(3), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(3)); -- Location: LC_X6_Y1_N5 \Ram_Control_Inst|Read_Data[3]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux5~0\ = (\bypass~regout\ & (((\AD_DA_Inst|ad_data\(3))))) # (!\bypass~regout\ & (((D1_Read_Data[3])))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa50", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, dataa => \bypass~regout\, datac => \Ram_Data[3]~3\, datad => \AD_DA_Inst|ad_data\(3), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux5~0\, regout => \Ram_Control_Inst|Read_Data\(3)); -- Location: LC_X6_Y1_N6 \AD_DA_Inst|DA_Out[3]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(3) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux5~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(3)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa0a", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \AD_DA_Inst|DA_Out\(3), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux5~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(3)); -- Location: PIN_29, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[4]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(4), combout => \AD_Data~combout\(4)); -- Location: LC_X6_Y1_N7 \AD_DA_Inst|ad_data[4]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(4) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_Data~combout\(4)))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|ad_data\(4)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|ad_data\(4), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_Data~combout\(4), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(4)); -- Location: LC_X6_Y1_N8 \Ram_Control_Inst|Read_Data[4]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux6~0\ = (\bypass~regout\ & (((\AD_DA_Inst|ad_data\(4))))) # (!\bypass~regout\ & (((D1_Read_Data[4])))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa50", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, dataa => \bypass~regout\, datac => \Ram_Data[4]~4\, datad => \AD_DA_Inst|ad_data\(4), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux6~0\, regout => \Ram_Control_Inst|Read_Data\(4)); -- Location: LC_X6_Y1_N9 \AD_DA_Inst|DA_Out[4]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(4) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux6~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(4)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|DA_Out\(4), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux6~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(4)); -- Location: PIN_28, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[5]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(5), combout => \AD_Data~combout\(5)); -- Location: LC_X7_Y1_N7 \AD_DA_Inst|ad_data[5]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(5) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_Data~combout\(5)))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|ad_data\(5)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|ad_data\(5), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_Data~combout\(5), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(5)); -- Location: LC_X7_Y1_N8 \Ram_Control_Inst|Read_Data[5]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux7~0\ = ((\bypass~regout\ & ((\AD_DA_Inst|ad_data\(5)))) # (!\bypass~regout\ & (D1_Read_Data[5]))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc30", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, datab => \bypass~regout\, datac => \Ram_Data[5]~5\, datad => \AD_DA_Inst|ad_data\(5), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux7~0\, regout => \Ram_Control_Inst|Read_Data\(5)); -- Location: LC_X7_Y1_N0 \AD_DA_Inst|DA_Out[5]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(5) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux7~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(5)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|DA_Out\(5), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux7~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(5)); -- Location: PIN_27, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[6]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(6), combout => \AD_Data~combout\(6)); -- Location: LC_X6_Y1_N1 \AD_DA_Inst|ad_data[6]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(6) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_Data~combout\(6))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|ad_data\(6))))) -- pragma translate_off GENERIC MAP ( lut_mask => "cfc0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_Data~combout\(6), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|ad_data\(6), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(6)); -- Location: LC_X6_Y1_N2 \Ram_Control_Inst|Read_Data[6]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux8~0\ = (\bypass~regout\ & (((\AD_DA_Inst|ad_data\(6))))) # (!\bypass~regout\ & (((D1_Read_Data[6])))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa50", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, dataa => \bypass~regout\, datac => \Ram_Data[6]~6\, datad => \AD_DA_Inst|ad_data\(6), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux8~0\, regout => \Ram_Control_Inst|Read_Data\(6)); -- Location: LC_X6_Y1_N0 \AD_DA_Inst|DA_Out[6]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(6) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux8~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(6)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \AD_DA_Inst|DA_Out\(6), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux8~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(6)); -- Location: PIN_26, I/O Standard: 3.3-V LVTTL, Current Strength: Default \AD_Data[7]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_AD_Data(7), combout => \AD_Data~combout\(7)); -- Location: LC_X7_Y1_N3 \AD_DA_Inst|ad_data[7]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|ad_data\(7) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_Data~combout\(7))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|ad_data\(7))))) -- pragma translate_off GENERIC MAP ( lut_mask => "afa0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \AD_Data~combout\(7), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|ad_data\(7), devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|ad_data\(7)); -- Location: LC_X7_Y1_N4 \Ram_Control_Inst|Read_Data[7]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|Mux9~0\ = ((\bypass~regout\ & ((\AD_DA_Inst|ad_data\(7)))) # (!\bypass~regout\ & (D1_Read_Data[7]))) -- pragma translate_off GENERIC MAP ( lut_mask => "fc30", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \ALT_INV_Clk~combout\, datab => \bypass~regout\, datac => \Ram_Data[7]~7\, datad => \AD_DA_Inst|ad_data\(7), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|load_enable~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|Mux9~0\, regout => \Ram_Control_Inst|Read_Data\(7)); -- Location: LC_X7_Y1_N5 \AD_DA_Inst|DA_Out[7]\ : maxii_lcell -- Equation(s): -- \AD_DA_Inst|DA_Out\(7) = ((GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & ((\AD_DA_Inst|Mux9~0\))) # (!GLOBAL(\AD_DA_Inst|Mux10~1_combout\) & (\AD_DA_Inst|DA_Out\(7)))) -- pragma translate_off GENERIC MAP ( lut_mask => "fa0a", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \AD_DA_Inst|DA_Out\(7), datac => \AD_DA_Inst|Mux10~1_combout\, datad => \AD_DA_Inst|Mux9~0\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \AD_DA_Inst|DA_Out\(7)); -- Location: PIN_12, I/O Standard: 3.3-V LVTTL, Current Strength: Default \Clk~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "input") -- pragma translate_on PORT MAP ( oe => GND, padio => ww_Clk, combout => \Clk~combout\); -- Location: LC_X2_Y2_N6 \Ram_Control_Inst|WideOr24~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr24~0_combout\ = (!\Ram_Control_Inst|ram_state.ram_read~regout\ & (((!\Ram_Control_Inst|ram_state.activate~regout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "0055", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.ram_read~regout\, datad => \Ram_Control_Inst|ram_state.activate~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr24~0_combout\); -- Location: LC_X3_Y4_N3 \Address_Counter_Inst|counter_count[0]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(0) = DFFEAS((!\Address_Counter_Inst|counter_count\(0)), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[0]~1\ = CARRY((\Address_Counter_Inst|counter_count\(0))) -- \Address_Counter_Inst|counter_count[0]~1COUT1_68\ = CARRY((\Address_Counter_Inst|counter_count\(0))) -- pragma translate_off GENERIC MAP ( lut_mask => "55aa", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(0), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(0), cout0 => \Address_Counter_Inst|counter_count[0]~1\, cout1 => \Address_Counter_Inst|counter_count[0]~1COUT1_68\); -- Location: LC_X4_Y1_N6 \Ram_Control_Inst|address_buf[0]~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf[0]~0_combout\ = (GLOBAL(\ResetN~combout\) & (((\Ram_Control_Inst|ram_state.precharge~regout\ & !\Ram_Control_Inst|another_refresh~regout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "00a0", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \ResetN~combout\, datac => \Ram_Control_Inst|ram_state.precharge~regout\, datad => \Ram_Control_Inst|another_refresh~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|address_buf[0]~0_combout\); -- Location: LC_X2_Y4_N6 \Ram_Control_Inst|address_buf[0]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(0) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(0), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(0), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(0)); -- Location: LC_X2_Y2_N2 \Ram_Control_Inst|address_temp[0]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(0) = DFFEAS((\Ram_Control_Inst|WideOr24~0_combout\ & (\Ram_Control_Inst|address_temp\(0) & (!\Ram_Control_Inst|ram_state.set_mode_register~regout\))) # (!\Ram_Control_Inst|WideOr24~0_combout\ & -- (((\Ram_Control_Inst|address_buf\(0))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "2f20", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|address_temp\(0), datab => \Ram_Control_Inst|ram_state.set_mode_register~regout\, datac => \Ram_Control_Inst|WideOr24~0_combout\, datad => \Ram_Control_Inst|address_buf\(0), aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(0)); -- Location: LC_X3_Y4_N4 \Address_Counter_Inst|counter_count[1]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(1) = DFFEAS(\Address_Counter_Inst|counter_count\(1) $ ((((\Address_Counter_Inst|counter_count[0]~1\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[1]~3\ = CARRY(((!\Address_Counter_Inst|counter_count[0]~1COUT1_68\)) # (!\Address_Counter_Inst|counter_count\(1))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(1), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin0 => \Address_Counter_Inst|counter_count[0]~1\, cin1 => \Address_Counter_Inst|counter_count[0]~1COUT1_68\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(1), cout => \Address_Counter_Inst|counter_count[1]~3\); -- Location: LC_X3_Y4_N1 \Ram_Control_Inst|address_buf[1]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(1) = DFFEAS((((\Address_Counter_Inst|counter_count\(1)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f0f0", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(1), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(1)); -- Location: LC_X2_Y2_N7 \Ram_Control_Inst|address_temp[1]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(1) = DFFEAS((\Ram_Control_Inst|WideOr24~0_combout\ & (((\Ram_Control_Inst|address_temp\(1) & !\Ram_Control_Inst|ram_state.set_mode_register~regout\)))) # (!\Ram_Control_Inst|WideOr24~0_combout\ & -- (\Ram_Control_Inst|address_buf\(1))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "0caa", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|address_buf\(1), datab => \Ram_Control_Inst|address_temp\(1), datac => \Ram_Control_Inst|ram_state.set_mode_register~regout\, datad => \Ram_Control_Inst|WideOr24~0_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(1)); -- Location: LC_X3_Y4_N5 \Address_Counter_Inst|counter_count[2]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(2) = DFFEAS(\Address_Counter_Inst|counter_count\(2) $ ((((!\Address_Counter_Inst|counter_count[1]~3\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[2]~7\ = CARRY((\Address_Counter_Inst|counter_count\(2) & ((!\Address_Counter_Inst|counter_count[1]~3\)))) -- \Address_Counter_Inst|counter_count[2]~7COUT1_70\ = CARRY((\Address_Counter_Inst|counter_count\(2) & ((!\Address_Counter_Inst|counter_count[1]~3\)))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "a50a", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(2), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[1]~3\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(2), cout0 => \Address_Counter_Inst|counter_count[2]~7\, cout1 => \Address_Counter_Inst|counter_count[2]~7COUT1_70\); -- Location: LC_X3_Y4_N2 \Ram_Control_Inst|address_buf[2]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(2) = DFFEAS((((\Address_Counter_Inst|counter_count\(2)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f0f0", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(2), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(2)); -- Location: LC_X3_Y4_N6 \Address_Counter_Inst|counter_count[3]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(3) = DFFEAS(\Address_Counter_Inst|counter_count\(3) $ (((((!\Address_Counter_Inst|counter_count[1]~3\ & \Address_Counter_Inst|counter_count[2]~7\) # (\Address_Counter_Inst|counter_count[1]~3\ & -- \Address_Counter_Inst|counter_count[2]~7COUT1_70\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[3]~11\ = CARRY(((!\Address_Counter_Inst|counter_count[2]~7\)) # (!\Address_Counter_Inst|counter_count\(3))) -- \Address_Counter_Inst|counter_count[3]~11COUT1_72\ = CARRY(((!\Address_Counter_Inst|counter_count[2]~7COUT1_70\)) # (!\Address_Counter_Inst|counter_count\(3))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(3), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[1]~3\, cin0 => \Address_Counter_Inst|counter_count[2]~7\, cin1 => \Address_Counter_Inst|counter_count[2]~7COUT1_70\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(3), cout0 => \Address_Counter_Inst|counter_count[3]~11\, cout1 => \Address_Counter_Inst|counter_count[3]~11COUT1_72\); -- Location: LC_X3_Y4_N7 \Address_Counter_Inst|counter_count[4]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(4) = DFFEAS((\Address_Counter_Inst|counter_count\(4) $ ((!(!\Address_Counter_Inst|counter_count[1]~3\ & \Address_Counter_Inst|counter_count[3]~11\) # (\Address_Counter_Inst|counter_count[1]~3\ & -- \Address_Counter_Inst|counter_count[3]~11COUT1_72\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[4]~15\ = CARRY(((\Address_Counter_Inst|counter_count\(4) & !\Address_Counter_Inst|counter_count[3]~11\))) -- \Address_Counter_Inst|counter_count[4]~15COUT1_74\ = CARRY(((\Address_Counter_Inst|counter_count\(4) & !\Address_Counter_Inst|counter_count[3]~11COUT1_72\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c30c", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(4), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[1]~3\, cin0 => \Address_Counter_Inst|counter_count[3]~11\, cin1 => \Address_Counter_Inst|counter_count[3]~11COUT1_72\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(4), cout0 => \Address_Counter_Inst|counter_count[4]~15\, cout1 => \Address_Counter_Inst|counter_count[4]~15COUT1_74\); -- Location: LC_X3_Y4_N8 \Address_Counter_Inst|counter_count[5]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(5) = DFFEAS(\Address_Counter_Inst|counter_count\(5) $ (((((!\Address_Counter_Inst|counter_count[1]~3\ & \Address_Counter_Inst|counter_count[4]~15\) # (\Address_Counter_Inst|counter_count[1]~3\ & -- \Address_Counter_Inst|counter_count[4]~15COUT1_74\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[5]~19\ = CARRY(((!\Address_Counter_Inst|counter_count[4]~15\)) # (!\Address_Counter_Inst|counter_count\(5))) -- \Address_Counter_Inst|counter_count[5]~19COUT1_76\ = CARRY(((!\Address_Counter_Inst|counter_count[4]~15COUT1_74\)) # (!\Address_Counter_Inst|counter_count\(5))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(5), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[1]~3\, cin0 => \Address_Counter_Inst|counter_count[4]~15\, cin1 => \Address_Counter_Inst|counter_count[4]~15COUT1_74\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(5), cout0 => \Address_Counter_Inst|counter_count[5]~19\, cout1 => \Address_Counter_Inst|counter_count[5]~19COUT1_76\); -- Location: LC_X3_Y4_N9 \Address_Counter_Inst|counter_count[6]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(6) = DFFEAS((\Address_Counter_Inst|counter_count\(6) $ ((!(!\Address_Counter_Inst|counter_count[1]~3\ & \Address_Counter_Inst|counter_count[5]~19\) # (\Address_Counter_Inst|counter_count[1]~3\ & -- \Address_Counter_Inst|counter_count[5]~19COUT1_76\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[6]~23\ = CARRY(((\Address_Counter_Inst|counter_count\(6) & !\Address_Counter_Inst|counter_count[5]~19COUT1_76\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c30c", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(6), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[1]~3\, cin0 => \Address_Counter_Inst|counter_count[5]~19\, cin1 => \Address_Counter_Inst|counter_count[5]~19COUT1_76\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(6), cout => \Address_Counter_Inst|counter_count[6]~23\); -- Location: LC_X4_Y4_N0 \Address_Counter_Inst|counter_count[7]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(7) = DFFEAS((\Address_Counter_Inst|counter_count\(7) $ ((\Address_Counter_Inst|counter_count[6]~23\))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[7]~27\ = CARRY(((!\Address_Counter_Inst|counter_count[6]~23\) # (!\Address_Counter_Inst|counter_count\(7)))) -- \Address_Counter_Inst|counter_count[7]~27COUT1_78\ = CARRY(((!\Address_Counter_Inst|counter_count[6]~23\) # (!\Address_Counter_Inst|counter_count\(7)))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "3c3f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(7), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[6]~23\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(7), cout0 => \Address_Counter_Inst|counter_count[7]~27\, cout1 => \Address_Counter_Inst|counter_count[7]~27COUT1_78\); -- Location: LC_X4_Y4_N1 \Address_Counter_Inst|counter_count[8]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(8) = DFFEAS((\Address_Counter_Inst|counter_count\(8) $ ((!(!\Address_Counter_Inst|counter_count[6]~23\ & \Address_Counter_Inst|counter_count[7]~27\) # (\Address_Counter_Inst|counter_count[6]~23\ & -- \Address_Counter_Inst|counter_count[7]~27COUT1_78\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[8]~31\ = CARRY(((\Address_Counter_Inst|counter_count\(8) & !\Address_Counter_Inst|counter_count[7]~27\))) -- \Address_Counter_Inst|counter_count[8]~31COUT1_80\ = CARRY(((\Address_Counter_Inst|counter_count\(8) & !\Address_Counter_Inst|counter_count[7]~27COUT1_78\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c30c", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(8), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[6]~23\, cin0 => \Address_Counter_Inst|counter_count[7]~27\, cin1 => \Address_Counter_Inst|counter_count[7]~27COUT1_78\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(8), cout0 => \Address_Counter_Inst|counter_count[8]~31\, cout1 => \Address_Counter_Inst|counter_count[8]~31COUT1_80\); -- Location: LC_X4_Y4_N2 \Address_Counter_Inst|counter_count[9]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(9) = DFFEAS((\Address_Counter_Inst|counter_count\(9) $ (((!\Address_Counter_Inst|counter_count[6]~23\ & \Address_Counter_Inst|counter_count[8]~31\) # (\Address_Counter_Inst|counter_count[6]~23\ & -- \Address_Counter_Inst|counter_count[8]~31COUT1_80\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[9]~35\ = CARRY(((!\Address_Counter_Inst|counter_count[8]~31\) # (!\Address_Counter_Inst|counter_count\(9)))) -- \Address_Counter_Inst|counter_count[9]~35COUT1_82\ = CARRY(((!\Address_Counter_Inst|counter_count[8]~31COUT1_80\) # (!\Address_Counter_Inst|counter_count\(9)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "3c3f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(9), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[6]~23\, cin0 => \Address_Counter_Inst|counter_count[8]~31\, cin1 => \Address_Counter_Inst|counter_count[8]~31COUT1_80\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(9), cout0 => \Address_Counter_Inst|counter_count[9]~35\, cout1 => \Address_Counter_Inst|counter_count[9]~35COUT1_82\); -- Location: LC_X4_Y4_N3 \Address_Counter_Inst|counter_count[10]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(10) = DFFEAS(\Address_Counter_Inst|counter_count\(10) $ ((((!(!\Address_Counter_Inst|counter_count[6]~23\ & \Address_Counter_Inst|counter_count[9]~35\) # (\Address_Counter_Inst|counter_count[6]~23\ & -- \Address_Counter_Inst|counter_count[9]~35COUT1_82\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[10]~39\ = CARRY((\Address_Counter_Inst|counter_count\(10) & ((!\Address_Counter_Inst|counter_count[9]~35\)))) -- \Address_Counter_Inst|counter_count[10]~39COUT1_84\ = CARRY((\Address_Counter_Inst|counter_count\(10) & ((!\Address_Counter_Inst|counter_count[9]~35COUT1_82\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "a50a", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(10), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[6]~23\, cin0 => \Address_Counter_Inst|counter_count[9]~35\, cin1 => \Address_Counter_Inst|counter_count[9]~35COUT1_82\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(10), cout0 => \Address_Counter_Inst|counter_count[10]~39\, cout1 => \Address_Counter_Inst|counter_count[10]~39COUT1_84\); -- Location: LC_X4_Y4_N4 \Address_Counter_Inst|counter_count[11]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(11) = DFFEAS(\Address_Counter_Inst|counter_count\(11) $ (((((!\Address_Counter_Inst|counter_count[6]~23\ & \Address_Counter_Inst|counter_count[10]~39\) # (\Address_Counter_Inst|counter_count[6]~23\ & -- \Address_Counter_Inst|counter_count[10]~39COUT1_84\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[11]~43\ = CARRY(((!\Address_Counter_Inst|counter_count[10]~39COUT1_84\)) # (!\Address_Counter_Inst|counter_count\(11))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(11), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[6]~23\, cin0 => \Address_Counter_Inst|counter_count[10]~39\, cin1 => \Address_Counter_Inst|counter_count[10]~39COUT1_84\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(11), cout => \Address_Counter_Inst|counter_count[11]~43\); -- Location: LC_X4_Y4_N5 \Address_Counter_Inst|counter_count[12]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(12) = DFFEAS(\Address_Counter_Inst|counter_count\(12) $ ((((!\Address_Counter_Inst|counter_count[11]~43\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[12]~5\ = CARRY((\Address_Counter_Inst|counter_count\(12) & ((!\Address_Counter_Inst|counter_count[11]~43\)))) -- \Address_Counter_Inst|counter_count[12]~5COUT1_86\ = CARRY((\Address_Counter_Inst|counter_count\(12) & ((!\Address_Counter_Inst|counter_count[11]~43\)))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "a50a", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(12), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[11]~43\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(12), cout0 => \Address_Counter_Inst|counter_count[12]~5\, cout1 => \Address_Counter_Inst|counter_count[12]~5COUT1_86\); -- Location: LC_X2_Y4_N9 \Ram_Control_Inst|address_buf[12]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(12) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(12), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(12), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(12)); -- Location: LC_X3_Y2_N7 \Ram_Control_Inst|WideOr24~1\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|WideOr24~1_combout\ = (\Ram_Control_Inst|ram_state.set_mode_register~regout\) # (((\Ram_Control_Inst|ram_state.ram_read~regout\) # (\Ram_Control_Inst|ram_state.activate~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "fffa", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.set_mode_register~regout\, datac => \Ram_Control_Inst|ram_state.ram_read~regout\, datad => \Ram_Control_Inst|ram_state.activate~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|WideOr24~1_combout\); -- Location: LC_X2_Y2_N8 \Ram_Control_Inst|address_temp[2]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(2) = DFFEAS((\Ram_Control_Inst|ram_state.activate~regout\ & (((\Ram_Control_Inst|address_buf\(12))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(2), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "aa00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(2), datad => \Ram_Control_Inst|address_buf\(12), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(2)); -- Location: LC_X2_Y4_N5 \Ram_Control_Inst|address_buf[3]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(3) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(3), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(3), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(3)); -- Location: LC_X4_Y4_N6 \Address_Counter_Inst|counter_count[13]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(13) = DFFEAS(\Address_Counter_Inst|counter_count\(13) $ (((((!\Address_Counter_Inst|counter_count[11]~43\ & \Address_Counter_Inst|counter_count[12]~5\) # (\Address_Counter_Inst|counter_count[11]~43\ & -- \Address_Counter_Inst|counter_count[12]~5COUT1_86\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[13]~9\ = CARRY(((!\Address_Counter_Inst|counter_count[12]~5\)) # (!\Address_Counter_Inst|counter_count\(13))) -- \Address_Counter_Inst|counter_count[13]~9COUT1_88\ = CARRY(((!\Address_Counter_Inst|counter_count[12]~5COUT1_86\)) # (!\Address_Counter_Inst|counter_count\(13))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(13), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[11]~43\, cin0 => \Address_Counter_Inst|counter_count[12]~5\, cin1 => \Address_Counter_Inst|counter_count[12]~5COUT1_86\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(13), cout0 => \Address_Counter_Inst|counter_count[13]~9\, cout1 => \Address_Counter_Inst|counter_count[13]~9COUT1_88\); -- Location: LC_X4_Y3_N3 \Ram_Control_Inst|address_buf[13]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(13) = DFFEAS((((\Address_Counter_Inst|counter_count\(13)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \Address_Counter_Inst|counter_count\(13), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(13)); -- Location: LC_X2_Y2_N4 \Ram_Control_Inst|address_temp[3]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(3) = DFFEAS((\Ram_Control_Inst|ram_state.activate~regout\ & (((\Ram_Control_Inst|address_buf\(13))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(3), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "aa00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(3), datad => \Ram_Control_Inst|address_buf\(13), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(3)); -- Location: LC_X2_Y4_N3 \Ram_Control_Inst|address_buf[4]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(4) = DFFEAS((((\Address_Counter_Inst|counter_count\(4)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \Address_Counter_Inst|counter_count\(4), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(4)); -- Location: LC_X4_Y4_N7 \Address_Counter_Inst|counter_count[14]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(14) = DFFEAS((\Address_Counter_Inst|counter_count\(14) $ ((!(!\Address_Counter_Inst|counter_count[11]~43\ & \Address_Counter_Inst|counter_count[13]~9\) # (\Address_Counter_Inst|counter_count[11]~43\ & -- \Address_Counter_Inst|counter_count[13]~9COUT1_88\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[14]~13\ = CARRY(((\Address_Counter_Inst|counter_count\(14) & !\Address_Counter_Inst|counter_count[13]~9\))) -- \Address_Counter_Inst|counter_count[14]~13COUT1_90\ = CARRY(((\Address_Counter_Inst|counter_count\(14) & !\Address_Counter_Inst|counter_count[13]~9COUT1_88\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c30c", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(14), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[11]~43\, cin0 => \Address_Counter_Inst|counter_count[13]~9\, cin1 => \Address_Counter_Inst|counter_count[13]~9COUT1_88\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(14), cout0 => \Address_Counter_Inst|counter_count[14]~13\, cout1 => \Address_Counter_Inst|counter_count[14]~13COUT1_90\); -- Location: LC_X2_Y4_N0 \Ram_Control_Inst|address_buf[14]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(14) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(14), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(14), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(14)); -- Location: LC_X2_Y2_N3 \Ram_Control_Inst|address_temp[4]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(4) = DFFEAS((\Ram_Control_Inst|ram_state.activate~regout\ & (((\Ram_Control_Inst|address_buf\(14))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(4), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "aa00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(4), datad => \Ram_Control_Inst|address_buf\(14), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(4)); -- Location: LC_X4_Y4_N8 \Address_Counter_Inst|counter_count[15]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(15) = DFFEAS(\Address_Counter_Inst|counter_count\(15) $ (((((!\Address_Counter_Inst|counter_count[11]~43\ & \Address_Counter_Inst|counter_count[14]~13\) # (\Address_Counter_Inst|counter_count[11]~43\ & -- \Address_Counter_Inst|counter_count[14]~13COUT1_90\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[15]~17\ = CARRY(((!\Address_Counter_Inst|counter_count[14]~13\)) # (!\Address_Counter_Inst|counter_count\(15))) -- \Address_Counter_Inst|counter_count[15]~17COUT1_92\ = CARRY(((!\Address_Counter_Inst|counter_count[14]~13COUT1_90\)) # (!\Address_Counter_Inst|counter_count\(15))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(15), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[11]~43\, cin0 => \Address_Counter_Inst|counter_count[14]~13\, cin1 => \Address_Counter_Inst|counter_count[14]~13COUT1_90\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(15), cout0 => \Address_Counter_Inst|counter_count[15]~17\, cout1 => \Address_Counter_Inst|counter_count[15]~17COUT1_92\); -- Location: LC_X2_Y4_N1 \Ram_Control_Inst|address_buf[15]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(15) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(15), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(15), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(15)); -- Location: LC_X2_Y4_N7 \Ram_Control_Inst|address_buf[5]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(5) = DFFEAS((((\Address_Counter_Inst|counter_count\(5)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \Address_Counter_Inst|counter_count\(5), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(5)); -- Location: LC_X2_Y2_N5 \Ram_Control_Inst|address_temp[5]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(5) = DFFEAS(((\Ram_Control_Inst|address_buf\(15) & ((\Ram_Control_Inst|ram_state.activate~regout\)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(5), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "cc00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|address_buf\(15), datac => \Ram_Control_Inst|address_buf\(5), datad => \Ram_Control_Inst|ram_state.activate~regout\, aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(5)); -- Location: LC_X3_Y4_N0 \Ram_Control_Inst|address_buf[6]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(6) = DFFEAS((((\Address_Counter_Inst|counter_count\(6)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \Address_Counter_Inst|counter_count\(6), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(6)); -- Location: LC_X4_Y4_N9 \Address_Counter_Inst|counter_count[16]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(16) = DFFEAS((\Address_Counter_Inst|counter_count\(16) $ ((!(!\Address_Counter_Inst|counter_count[11]~43\ & \Address_Counter_Inst|counter_count[15]~17\) # (\Address_Counter_Inst|counter_count[11]~43\ & -- \Address_Counter_Inst|counter_count[15]~17COUT1_92\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[16]~21\ = CARRY(((\Address_Counter_Inst|counter_count\(16) & !\Address_Counter_Inst|counter_count[15]~17COUT1_92\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c30c", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(16), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[11]~43\, cin0 => \Address_Counter_Inst|counter_count[15]~17\, cin1 => \Address_Counter_Inst|counter_count[15]~17COUT1_92\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(16), cout => \Address_Counter_Inst|counter_count[16]~21\); -- Location: LC_X4_Y3_N9 \Ram_Control_Inst|address_buf[16]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(16) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(16), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(16), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(16)); -- Location: LC_X3_Y2_N3 \Ram_Control_Inst|address_temp[6]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(6) = DFFEAS((((\Ram_Control_Inst|address_buf\(16))) # (!\Ram_Control_Inst|ram_state.activate~regout\)), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(6), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "ff33", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(6), datad => \Ram_Control_Inst|address_buf\(16), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(6)); -- Location: LC_X4_Y3_N8 \Ram_Control_Inst|address_buf[7]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(7) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(7), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(7), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(7)); -- Location: LC_X5_Y4_N0 \Address_Counter_Inst|counter_count[17]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(17) = DFFEAS((\Address_Counter_Inst|counter_count\(17) $ ((\Address_Counter_Inst|counter_count[16]~21\))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[17]~25\ = CARRY(((!\Address_Counter_Inst|counter_count[16]~21\) # (!\Address_Counter_Inst|counter_count\(17)))) -- \Address_Counter_Inst|counter_count[17]~25COUT1_94\ = CARRY(((!\Address_Counter_Inst|counter_count[16]~21\) # (!\Address_Counter_Inst|counter_count\(17)))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "3c3f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(17), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[16]~21\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(17), cout0 => \Address_Counter_Inst|counter_count[17]~25\, cout1 => \Address_Counter_Inst|counter_count[17]~25COUT1_94\); -- Location: LC_X5_Y4_N8 \Ram_Control_Inst|address_buf[17]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(17) = DFFEAS((((\Address_Counter_Inst|counter_count\(17)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f0f0", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(17), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(17)); -- Location: LC_X2_Y2_N9 \Ram_Control_Inst|address_temp[7]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(7) = DFFEAS((((\Ram_Control_Inst|address_buf\(17)))) # (!\Ram_Control_Inst|ram_state.activate~regout\), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(7), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "ff55", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(7), datad => \Ram_Control_Inst|address_buf\(17), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(7)); -- Location: LC_X2_Y4_N8 \Ram_Control_Inst|address_buf[8]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(8) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(8), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(8), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(8)); -- Location: LC_X5_Y4_N1 \Address_Counter_Inst|counter_count[18]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(18) = DFFEAS((\Address_Counter_Inst|counter_count\(18) $ ((!(!\Address_Counter_Inst|counter_count[16]~21\ & \Address_Counter_Inst|counter_count[17]~25\) # (\Address_Counter_Inst|counter_count[16]~21\ & -- \Address_Counter_Inst|counter_count[17]~25COUT1_94\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[18]~29\ = CARRY(((\Address_Counter_Inst|counter_count\(18) & !\Address_Counter_Inst|counter_count[17]~25\))) -- \Address_Counter_Inst|counter_count[18]~29COUT1_96\ = CARRY(((\Address_Counter_Inst|counter_count\(18) & !\Address_Counter_Inst|counter_count[17]~25COUT1_94\))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "c30c", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(18), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[16]~21\, cin0 => \Address_Counter_Inst|counter_count[17]~25\, cin1 => \Address_Counter_Inst|counter_count[17]~25COUT1_94\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(18), cout0 => \Address_Counter_Inst|counter_count[18]~29\, cout1 => \Address_Counter_Inst|counter_count[18]~29COUT1_96\); -- Location: LC_X2_Y4_N2 \Ram_Control_Inst|address_buf[18]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(18) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(18), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(18), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(18)); -- Location: LC_X2_Y2_N1 \Ram_Control_Inst|address_temp[8]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(8) = DFFEAS((\Ram_Control_Inst|ram_state.activate~regout\ & (((\Ram_Control_Inst|address_buf\(18))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(8), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "aa00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(8), datad => \Ram_Control_Inst|address_buf\(18), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(8)); -- Location: LC_X2_Y4_N4 \Ram_Control_Inst|address_buf[9]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(9) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(9), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(9), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(9)); -- Location: LC_X5_Y4_N2 \Address_Counter_Inst|counter_count[19]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(19) = DFFEAS((\Address_Counter_Inst|counter_count\(19) $ (((!\Address_Counter_Inst|counter_count[16]~21\ & \Address_Counter_Inst|counter_count[18]~29\) # (\Address_Counter_Inst|counter_count[16]~21\ & -- \Address_Counter_Inst|counter_count[18]~29COUT1_96\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[19]~33\ = CARRY(((!\Address_Counter_Inst|counter_count[18]~29\) # (!\Address_Counter_Inst|counter_count\(19)))) -- \Address_Counter_Inst|counter_count[19]~33COUT1_98\ = CARRY(((!\Address_Counter_Inst|counter_count[18]~29COUT1_96\) # (!\Address_Counter_Inst|counter_count\(19)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "3c3f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datab => \Address_Counter_Inst|counter_count\(19), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[16]~21\, cin0 => \Address_Counter_Inst|counter_count[18]~29\, cin1 => \Address_Counter_Inst|counter_count[18]~29COUT1_96\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(19), cout0 => \Address_Counter_Inst|counter_count[19]~33\, cout1 => \Address_Counter_Inst|counter_count[19]~33COUT1_98\); -- Location: LC_X4_Y3_N7 \Ram_Control_Inst|address_buf[19]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(19) = DFFEAS((((\Address_Counter_Inst|counter_count\(19)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \Address_Counter_Inst|counter_count\(19), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(19)); -- Location: LC_X2_Y2_N0 \Ram_Control_Inst|address_temp[9]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(9) = DFFEAS((\Ram_Control_Inst|ram_state.activate~regout\ & (((\Ram_Control_Inst|address_buf\(19))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(9), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "aa00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(9), datad => \Ram_Control_Inst|address_buf\(19), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(9)); -- Location: LC_X4_Y3_N0 \Ram_Control_Inst|address_buf[10]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(10) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(10), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(10), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(10)); -- Location: LC_X5_Y4_N3 \Address_Counter_Inst|counter_count[20]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(20) = DFFEAS(\Address_Counter_Inst|counter_count\(20) $ ((((!(!\Address_Counter_Inst|counter_count[16]~21\ & \Address_Counter_Inst|counter_count[19]~33\) # (\Address_Counter_Inst|counter_count[16]~21\ & -- \Address_Counter_Inst|counter_count[19]~33COUT1_98\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[20]~37\ = CARRY((\Address_Counter_Inst|counter_count\(20) & ((!\Address_Counter_Inst|counter_count[19]~33\)))) -- \Address_Counter_Inst|counter_count[20]~37COUT1_100\ = CARRY((\Address_Counter_Inst|counter_count\(20) & ((!\Address_Counter_Inst|counter_count[19]~33COUT1_98\)))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "a50a", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(20), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[16]~21\, cin0 => \Address_Counter_Inst|counter_count[19]~33\, cin1 => \Address_Counter_Inst|counter_count[19]~33COUT1_98\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(20), cout0 => \Address_Counter_Inst|counter_count[20]~37\, cout1 => \Address_Counter_Inst|counter_count[20]~37COUT1_100\); -- Location: LC_X5_Y4_N7 \Ram_Control_Inst|address_buf[20]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(20) = DFFEAS((((\Address_Counter_Inst|counter_count\(20)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datad => \Address_Counter_Inst|counter_count\(20), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(20)); -- Location: LC_X3_Y2_N0 \Ram_Control_Inst|address_temp[10]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(10) = DFFEAS(((\Ram_Control_Inst|ram_state.activate~regout\ & ((\Ram_Control_Inst|address_buf\(20))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(10), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "cc00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(10), datad => \Ram_Control_Inst|address_buf\(20), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(10)); -- Location: LC_X4_Y3_N1 \Ram_Control_Inst|address_buf[11]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(11) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(11), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(11), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(11)); -- Location: LC_X5_Y4_N4 \Address_Counter_Inst|counter_count[21]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(21) = DFFEAS(\Address_Counter_Inst|counter_count\(21) $ (((((!\Address_Counter_Inst|counter_count[16]~21\ & \Address_Counter_Inst|counter_count[20]~37\) # (\Address_Counter_Inst|counter_count[16]~21\ & -- \Address_Counter_Inst|counter_count[20]~37COUT1_100\))))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[21]~41\ = CARRY(((!\Address_Counter_Inst|counter_count[20]~37COUT1_100\)) # (!\Address_Counter_Inst|counter_count\(21))) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "5a5f", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(21), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[16]~21\, cin0 => \Address_Counter_Inst|counter_count[20]~37\, cin1 => \Address_Counter_Inst|counter_count[20]~37COUT1_100\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(21), cout => \Address_Counter_Inst|counter_count[21]~41\); -- Location: LC_X4_Y3_N2 \Ram_Control_Inst|address_buf[21]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(21) = DFFEAS(GND, GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, \Address_Counter_Inst|counter_count\(21), , , VCC) -- pragma translate_off GENERIC MAP ( lut_mask => "0000", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(21), aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(21)); -- Location: LC_X3_Y2_N4 \Ram_Control_Inst|address_temp[11]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(11) = DFFEAS(((\Ram_Control_Inst|ram_state.activate~regout\ & ((\Ram_Control_Inst|address_buf\(21))))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , \Ram_Control_Inst|WideOr24~1_combout\, -- \Ram_Control_Inst|address_buf\(11), , , \Ram_Control_Inst|ram_state.ram_read~regout\) -- pragma translate_off GENERIC MAP ( lut_mask => "cc00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(11), datad => \Ram_Control_Inst|address_buf\(21), aclr => \ALT_INV_ResetN~combout\, sload => \Ram_Control_Inst|ram_state.ram_read~regout\, ena => \Ram_Control_Inst|WideOr24~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(11)); -- Location: LC_X5_Y4_N5 \Address_Counter_Inst|counter_count[22]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(22) = DFFEAS(\Address_Counter_Inst|counter_count\(22) $ ((((!\Address_Counter_Inst|counter_count[21]~41\)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- \Address_Counter_Inst|counter_count[22]~45\ = CARRY((\Address_Counter_Inst|counter_count\(22) & ((!\Address_Counter_Inst|counter_count[21]~41\)))) -- \Address_Counter_Inst|counter_count[22]~45COUT1_102\ = CARRY((\Address_Counter_Inst|counter_count\(22) & ((!\Address_Counter_Inst|counter_count[21]~41\)))) -- pragma translate_off GENERIC MAP ( cin_used => "true", lut_mask => "a50a", operation_mode => "arithmetic", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, dataa => \Address_Counter_Inst|counter_count\(22), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[21]~41\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(22), cout0 => \Address_Counter_Inst|counter_count[22]~45\, cout1 => \Address_Counter_Inst|counter_count[22]~45COUT1_102\); -- Location: LC_X4_Y3_N4 \Ram_Control_Inst|address_buf[22]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector30~1\ = (\Ram_Control_Inst|ram_state.precharge~regout\ & ((\Ram_Control_Inst|another_refresh~regout\) # ((D1_address_buf[22] & \Ram_Control_Inst|ram_state.activate~regout\)))) # (!\Ram_Control_Inst|ram_state.precharge~regout\ & -- (((D1_address_buf[22] & \Ram_Control_Inst|ram_state.activate~regout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "f888", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "qfbk", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.precharge~regout\, datab => \Ram_Control_Inst|another_refresh~regout\, datac => \Address_Counter_Inst|counter_count\(22), datad => \Ram_Control_Inst|ram_state.activate~regout\, aclr => GND, sload => VCC, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector30~1\, regout => \Ram_Control_Inst|address_buf\(22)); -- Location: LC_X3_Y3_N4 \Ram_Control_Inst|Selector30~2\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector30~2_combout\ = ((!\Ram_Control_Inst|ram_state.precharge~regout\ & (!\Ram_Control_Inst|ram_state.set_mode_register~regout\ & !\Ram_Control_Inst|ram_state.activate~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "0003", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datab => \Ram_Control_Inst|ram_state.precharge~regout\, datac => \Ram_Control_Inst|ram_state.set_mode_register~regout\, datad => \Ram_Control_Inst|ram_state.activate~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector30~2_combout\); -- Location: LC_X4_Y3_N5 \Ram_Control_Inst|address_temp[12]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(12) = DFFEAS((\Ram_Control_Inst|Selector30~1\) # ((\Ram_Control_Inst|address_temp\(12) & (!\Ram_Control_Inst|ram_state.ram_read~regout\ & \Ram_Control_Inst|Selector30~2_combout\))), GLOBAL(\Clk~combout\), -- GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f2f0", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|address_temp\(12), datab => \Ram_Control_Inst|ram_state.ram_read~regout\, datac => \Ram_Control_Inst|Selector30~1\, datad => \Ram_Control_Inst|Selector30~2_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(12)); -- Location: LC_X5_Y4_N6 \Address_Counter_Inst|counter_count[23]\ : maxii_lcell -- Equation(s): -- \Address_Counter_Inst|counter_count\(23) = DFFEAS((((!\Address_Counter_Inst|counter_count[21]~41\ & \Address_Counter_Inst|counter_count[22]~45\) # (\Address_Counter_Inst|counter_count[21]~41\ & \Address_Counter_Inst|counter_count[22]~45COUT1_102\) $ -- (\Address_Counter_Inst|counter_count\(23)))), GLOBAL(\rtl~0_combout\), GLOBAL(\ResetN~combout\), , , , , !\Address_Counter_Inst|LessThan0~0_combout\, ) -- pragma translate_off GENERIC MAP ( cin0_used => "true", cin1_used => "true", cin_used => "true", lut_mask => "0ff0", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "cin", synch_mode => "on") -- pragma translate_on PORT MAP ( clk => \rtl~0_combout\, datad => \Address_Counter_Inst|counter_count\(23), aclr => \ALT_INV_ResetN~combout\, sclr => \Address_Counter_Inst|ALT_INV_LessThan0~0_combout\, cin => \Address_Counter_Inst|counter_count[21]~41\, cin0 => \Address_Counter_Inst|counter_count[22]~45\, cin1 => \Address_Counter_Inst|counter_count[22]~45COUT1_102\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Address_Counter_Inst|counter_count\(23)); -- Location: LC_X5_Y4_N9 \Ram_Control_Inst|address_buf[23]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_buf\(23) = DFFEAS((((\Address_Counter_Inst|counter_count\(23)))), GLOBAL(\Clk~combout\), VCC, , \Ram_Control_Inst|address_buf[0]~0_combout\, , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f0f0", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datac => \Address_Counter_Inst|counter_count\(23), aclr => GND, ena => \Ram_Control_Inst|address_buf[0]~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_buf\(23)); -- Location: LC_X4_Y3_N6 \Ram_Control_Inst|address_temp[13]\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|address_temp\(13) = DFFEAS((\Ram_Control_Inst|address_temp\(13) & (((\Ram_Control_Inst|ram_state.activate~regout\ & \Ram_Control_Inst|address_buf\(23))) # (!\Ram_Control_Inst|WideOr24~1_combout\))) # (!\Ram_Control_Inst|address_temp\(13) -- & (\Ram_Control_Inst|ram_state.activate~regout\ & (\Ram_Control_Inst|address_buf\(23)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "c0ea", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|address_temp\(13), datab => \Ram_Control_Inst|ram_state.activate~regout\, datac => \Ram_Control_Inst|address_buf\(23), datad => \Ram_Control_Inst|WideOr24~1_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|address_temp\(13)); -- Location: LC_X3_Y3_N5 \Ram_Control_Inst|Ram_RAS\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Ram_RAS~regout\ = DFFEAS((\Ram_Control_Inst|ram_state.init~regout\ & (!\Ram_Control_Inst|ram_state.auto_refresh~regout\ & ((\Ram_Control_Inst|Selector30~2_combout\)))) # (!\Ram_Control_Inst|ram_state.init~regout\ & -- (((\Ram_Control_Inst|Ram_RAS~regout\)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "7430", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datab => \Ram_Control_Inst|ram_state.init~regout\, datac => \Ram_Control_Inst|Ram_RAS~regout\, datad => \Ram_Control_Inst|Selector30~2_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|Ram_RAS~regout\); -- Location: LC_X2_Y1_N1 we : maxii_lcell -- Equation(s): -- \we~regout\ = DFFEAS(((\Rec_Button~combout\ & ((\Rec_Switch~combout\)))), \V_Sync~combout\, GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "cc00", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \V_Sync~combout\, datab => \Rec_Button~combout\, datad => \Rec_Switch~combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \we~regout\); -- Location: LC_X2_Y1_N8 \Ram_Control_Inst|Selector1~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector1~0_combout\ = (\Ram_Control_Inst|ram_state.ram_write~regout\ & ((\we~regout\) # ((\Ram_Control_Inst|Ram_CAS~regout\ & !\Ram_Control_Inst|ram_state.init~regout\)))) # (!\Ram_Control_Inst|ram_state.ram_write~regout\ & -- (\Ram_Control_Inst|Ram_CAS~regout\ & (!\Ram_Control_Inst|ram_state.init~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "ae0c", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.ram_write~regout\, datab => \Ram_Control_Inst|Ram_CAS~regout\, datac => \Ram_Control_Inst|ram_state.init~regout\, datad => \we~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector1~0_combout\); -- Location: LC_X2_Y1_N9 \Ram_Control_Inst|Ram_CAS\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Ram_CAS~regout\ = DFFEAS((\Ram_Control_Inst|Selector1~0_combout\) # ((!\Ram_Control_Inst|ram_state.auto_refresh~regout\ & (!\Ram_Control_Inst|ram_state.ram_read~regout\ & \Ram_Control_Inst|WideOr2~0_combout\))), GLOBAL(\Clk~combout\), -- GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff10", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|ram_state.auto_refresh~regout\, datab => \Ram_Control_Inst|ram_state.ram_read~regout\, datac => \Ram_Control_Inst|WideOr2~0_combout\, datad => \Ram_Control_Inst|Selector1~0_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|Ram_CAS~regout\); -- Location: LC_X2_Y1_N3 \Ram_Control_Inst|Selector2~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector2~0_combout\ = (\Ram_Control_Inst|ram_state.init~regout\ & (\Ram_Control_Inst|ram_state.ram_write~regout\ & ((\we~regout\)))) # (!\Ram_Control_Inst|ram_state.init~regout\ & ((\Ram_Control_Inst|Ram_WE~regout\) # -- ((\Ram_Control_Inst|ram_state.ram_write~regout\ & \we~regout\)))) -- pragma translate_off GENERIC MAP ( lut_mask => "dc50", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( dataa => \Ram_Control_Inst|ram_state.init~regout\, datab => \Ram_Control_Inst|ram_state.ram_write~regout\, datac => \Ram_Control_Inst|Ram_WE~regout\, datad => \we~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector2~0_combout\); -- Location: LC_X2_Y1_N4 \Ram_Control_Inst|Ram_WE\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Ram_WE~regout\ = DFFEAS(((\Ram_Control_Inst|Selector2~0_combout\) # ((!\Ram_Control_Inst|ram_state.precharge~regout\ & \Ram_Control_Inst|WideOr2~0_combout\))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "ff30", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.precharge~regout\, datac => \Ram_Control_Inst|WideOr2~0_combout\, datad => \Ram_Control_Inst|Selector2~0_combout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|Ram_WE~regout\); -- Location: LC_X2_Y3_N2 \Ram_Control_Inst|Selector3~0\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Selector3~0_combout\ = (((!\Ram_Control_Inst|ram_state.ram_read~regout\ & !\Ram_Control_Inst|ram_state.ram_write~regout\))) -- pragma translate_off GENERIC MAP ( lut_mask => "000f", operation_mode => "normal", output_mode => "comb_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( datac => \Ram_Control_Inst|ram_state.ram_read~regout\, datad => \Ram_Control_Inst|ram_state.ram_write~regout\, devclrn => ww_devclrn, devpor => ww_devpor, combout => \Ram_Control_Inst|Selector3~0_combout\); -- Location: LC_X2_Y3_N7 \Ram_Control_Inst|Ram_DQM\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|Ram_DQM~regout\ = DFFEAS((\Ram_Control_Inst|ram_state.nop~regout\) # (((\Ram_Control_Inst|Ram_DQM~regout\ & \Ram_Control_Inst|Selector3~0_combout\)) # (!\Ram_Control_Inst|ram_state.init~regout\)), GLOBAL(\Clk~combout\), VCC, , -- GLOBAL(\ResetN~combout\), , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "f8ff", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, dataa => \Ram_Control_Inst|Ram_DQM~regout\, datab => \Ram_Control_Inst|Selector3~0_combout\, datac => \Ram_Control_Inst|ram_state.nop~regout\, datad => \Ram_Control_Inst|ram_state.init~regout\, aclr => GND, ena => \ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|Ram_DQM~regout\); -- Location: LC_X2_Y3_N1 \Ram_Control_Inst|OEn\ : maxii_lcell -- Equation(s): -- \Ram_Control_Inst|OEn~regout\ = DFFEAS(((!\Ram_Control_Inst|ram_state.ram_read~regout\ & ((\Ram_Control_Inst|ram_state.toggle_OE~regout\) # (\Ram_Control_Inst|OEn~regout\)))), GLOBAL(\Clk~combout\), GLOBAL(\ResetN~combout\), , , , , , ) -- pragma translate_off GENERIC MAP ( lut_mask => "0f0c", operation_mode => "normal", output_mode => "reg_only", register_cascade_mode => "off", sum_lutc_input => "datac", synch_mode => "off") -- pragma translate_on PORT MAP ( clk => \Clk~combout\, datab => \Ram_Control_Inst|ram_state.toggle_OE~regout\, datac => \Ram_Control_Inst|ram_state.ram_read~regout\, datad => \Ram_Control_Inst|OEn~regout\, aclr => \ALT_INV_ResetN~combout\, devclrn => ww_devclrn, devpor => ww_devpor, regout => \Ram_Control_Inst|OEn~regout\); -- Location: PIN_19, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Led1~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Rec_Switch~combout\, oe => VCC, padio => ww_Led1); -- Location: PIN_20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Led2~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => GND, oe => VCC, padio => ww_Led2); -- Location: PIN_21, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Led3~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Rec_Button~combout\, oe => VCC, padio => ww_Led3); -- Location: PIN_67, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Led_Front~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Address_Counter_Inst|counter_did_reset~regout\, oe => VCC, padio => ww_Led_Front); -- Location: PIN_36, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \AD_Clk~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|AD_Clk~combout\, oe => VCC, padio => ww_AD_Clk); -- Location: PIN_47, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Clk~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|AD_Clk~combout\, oe => VCC, padio => ww_DA_Clk); -- Location: PIN_44, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[0]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(0), oe => VCC, padio => ww_DA_Data(0)); -- Location: PIN_43, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[1]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(1), oe => VCC, padio => ww_DA_Data(1)); -- Location: PIN_42, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[2]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(2), oe => VCC, padio => ww_DA_Data(2)); -- Location: PIN_41, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[3]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(3), oe => VCC, padio => ww_DA_Data(3)); -- Location: PIN_40, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[4]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(4), oe => VCC, padio => ww_DA_Data(4)); -- Location: PIN_39, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[5]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(5), oe => VCC, padio => ww_DA_Data(5)); -- Location: PIN_38, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[6]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(6), oe => VCC, padio => ww_DA_Data(6)); -- Location: PIN_37, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \DA_Data[7]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \AD_DA_Inst|DA_Out\(7), oe => VCC, padio => ww_DA_Data(7)); -- Location: PIN_96, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[0]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(0), oe => VCC, padio => ww_Ram_Address(0)); -- Location: PIN_95, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[1]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(1), oe => VCC, padio => ww_Ram_Address(1)); -- Location: PIN_89, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[2]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(2), oe => VCC, padio => ww_Ram_Address(2)); -- Location: PIN_90, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[3]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(3), oe => VCC, padio => ww_Ram_Address(3)); -- Location: PIN_91, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[4]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(4), oe => VCC, padio => ww_Ram_Address(4)); -- Location: PIN_92, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[5]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(5), oe => VCC, padio => ww_Ram_Address(5)); -- Location: PIN_81, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[6]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(6), oe => VCC, padio => ww_Ram_Address(6)); -- Location: PIN_82, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[7]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(7), oe => VCC, padio => ww_Ram_Address(7)); -- Location: PIN_83, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[8]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(8), oe => VCC, padio => ww_Ram_Address(8)); -- Location: PIN_84, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[9]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(9), oe => VCC, padio => ww_Ram_Address(9)); -- Location: PIN_85, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[10]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(10), oe => VCC, padio => ww_Ram_Address(10)); -- Location: PIN_86, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[11]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(11), oe => VCC, padio => ww_Ram_Address(11)); -- Location: PIN_88, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[12]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(12), oe => VCC, padio => ww_Ram_Address(12)); -- Location: PIN_87, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Address[13]~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|address_temp\(13), oe => VCC, padio => ww_Ram_Address(13)); -- Location: PIN_97, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_RAS~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|Ram_RAS~regout\, oe => VCC, padio => ww_Ram_RAS); -- Location: PIN_98, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_CAS~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|Ram_CAS~regout\, oe => VCC, padio => ww_Ram_CAS); -- Location: PIN_99, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_WE~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|Ram_WE~regout\, oe => VCC, padio => ww_Ram_WE); -- Location: PIN_78, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_Clk~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \ALT_INV_Clk~combout\, oe => VCC, padio => ww_Ram_Clk); -- Location: PIN_77, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \Ram_DQM~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => \Ram_Control_Inst|Ram_DQM~regout\, oe => VCC, padio => ww_Ram_DQM); -- Location: PIN_70, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA \MISO~I\ : maxii_io -- pragma translate_off GENERIC MAP ( operation_mode => "output") -- pragma translate_on PORT MAP ( datain => GND, oe => VCC, padio => ww_MISO); END structure;