LIBRARY ieee; USE ieee.std_logic_1164.all; entity test_tb is end test_tb; architecture test_tb_a of test_tb is signal Clk : std_logic; signal ResetN : std_logic; signal Overflow : std_logic; signal V_Sync : std_logic; signal Rec : std_logic; component test port ( Clk : in std_logic; ResetN : in std_logic; Overflow : out std_logic; V_Sync : in std_logic; Rec : in std_logic ); end component; begin t1 : test port map ( Clk => Clk, ResetN => ResetN, Overflow => Overflow, V_Sync => V_Sync, Rec => Rec ); init: process begin ResetN <= '0'; wait for 50 ns; ResetN <= '1'; wait; end process; always: process begin loop Clk <= '0'; wait for 10 ns; Clk <= '1'; wait for 10 ns; end loop; WAIT; end process; vsync: process begin loop V_Sync <= '0'; wait for 153 ns; V_Sync <= '1'; wait for 53 ns; end loop; WAIT; end process; button : process begin Rec <= '0'; wait for 222 ns; Rec <= '1'; wait for 633 ns; Rec <= '0'; wait; end process; end test_tb_a;